Publications (complete list)

Journal

K.-P. Lin, Y.-C. Ding, C.-Y. Lin, Y.-T. Chen, and C.-T. Huang, "CINE: A 4K-UHD Energy-Efficient Computational Imaging Neural Engine with Overlapped Stripe Inference and Structure-Sparse Kernel ," IEEE Solid-State Circuits Letters, vol. 7, pp26-29, 2024.

P.-H. Chen, Y.-W. Yang, and C.-T. Huang, "A 250mW 5.4G-Rendered-Pixel/s Realistic Refocusing Processor for High-Performance Five-Camera Mobile Devices," IEEE Open Journal of the Solid-State Circuits Society, vol. 3, pp52-62, Feb 2023.

C.-T. Chiu, Y.-C. Ding, W.-C. Lin, W.-J. Chen, S.-Y. Wu, C.-T. Huang, C.-Y. Lin, C.-Y. Chang, M.-J. Lee, S. Tatsunori, T. Chen, F.-Y. Lin, and Y.-H. Huang, "Chaos LiDAR Based RGB-D Face Classification System with Embedded CNN Accelerator on FPGAs," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 12, pp4847-4859, Dec 2022.

C.-C. Wang, Y.-C. Ding, C.-T. Chiu, C.-T. Huang, Y.-Y. Cheng, S.-Y., Sun, C.-H. Cheng, and H.-K. Kuo, "Real-time Block-based Embedded CNN for Gesture Classification on an FPGA," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 10, pp4182-4193, Oct 2021.

C.-T. Huang, "Empirical Bayesian Light-Field Stereo Matching by Robust Pseudo Random Field Modeling," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 41, no. 3, pp552-565, Mar 2019. [web]

C.-T. Huang, Y.-W. Wang, L.-R. Huang, J. Chin, and L.-G. Chen, "Fast Physically-Correct Refocusing for Sparse Light Fields Using Block-Based Multi-Rate View Interpolation," IEEE Transactions on Image Processing, vol. 26, no. 2, pp603-618, Feb 2017. [web]

C.-T. Huang, "Fast Distribution Fitting for Parameter Estimation of Range-Weighted Neighborhood Filters," IEEE Signal Processing Letters, vol. 23, no. 3, pp331-335, Mar 2016. [web]

C.-T. Huang, "Bayesian Inference for Neighborhood Filters with Application in Denoising," IEEE Transactions on Image Processing, vol. 24, no. 11, pp4299-4311, Nov 2015. [web]

C.-T. Huang, M. Tikekar, and A. Chandrakasan, "Memory-Hierarchical and Mode-Adaptive HEVC Intra Prediction Architecture for Quad Full HD Video Decoding," IEEE Transactions on Very Large Scale Integration Systems, vol. 22, no. 7, pp1515-1525, July 2014.

M. Tikekar, C.-T. Huang, C. Juvekar, V. Sze, and A. Chandrakasan, "A 249Mpixel/s HEVC Video-Decoder Chip for 4K Ultra HD Applications," IEEE Journal of Solid-State Circuits, vol. 49, no. 1, pp61-79, Jan 2014.

C.-C. Cheng, C.-T. Huang, C.-Y. Chen, C.-J. Lian, and L.-G. Chen, "On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimensional Discrete Wavelet Transform," IEEE Transactions on Circuits and Systems for Video Technology, vol. 17, no. 7, pp814-822, July 2007.

C.-Y. Chen, C.-T. Huang, Y.-H. Chen, S.-Y. Chien, and L.-G. Chen, "System Analysis of VLSI Architecture for 5/3 and 1/3 Motion-Compensated Temporal Filtering," IEEE Transactions on Signal Processing, vol. 54, no. 10, pp4004-4014, Oct 2006.

C.-Y. Chen, C.-T. Huang, Y.-H. Chen, and L.-G. Chen, "Level C+ Data Reuse Scheme for Motion Estimation with Corresponding Coding Order," IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, no. 4, pp553-558, April 2006.

H.-C. Fang, Y.-W. Chang, T.-C. Wang, C.-T. Huang, and L.-G. Chen, "High Performance JPEG 2000 Encoder with Rate-Distortion Optimization," IEEE Transactions on Multimedia, vol. 8 no. 4, pp645-653, Aug 2006.

C.-T. Huang, P.-C. Tseng, and L.-G. Chen, "Analysis and VLSI Architecture for 1-D and 2-D Discrete Wavelet Transform," IEEE Transactions on Signal Processing, vol. 53, no. 4, pp1575-1586, April 2005.

P.-C. Tseng, Y.-C. Chang, Y.-W. Huang, H.-C. Fang, C.-T. Huang, and L.-G. Chen, "Advances in Hardware Architectures for Image and Video Coding – A Survey," Proceedings of the IEEE, vol. 93, no. 1, pp184-197, Jan 2005.

P.-C. Tseng, C.-T. Huang, and L.-G. Chen, "Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems," Journal of VLSI Signal Processing Systems, vol. 41, pp35-47, 2005.

C.-T. Huang, P.-C. Tseng, and L.-G. Chen, "VLSI Architecture for Lifting-based Shape-Adaptive Discrete Wavelet Transform with Odd-symmetric Filters," Journal of VLSI Signal Processing Systems, vol. 40, pp175-188, 2005.

C.-T. Huang, P.-C. Tseng, and L.-G. Chen, "Generic RAM-Based Architectures for Two-Dimensional Discrete Wavelet Transform with Line-Based Method," IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 7, pp910-920, July 2005.

C.-T. Huang, P.-C. Tseng, and L.-G. Chen, "VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization," Journal of VLSI Signal Processing Systems, vol. 40, pp343-353, 2005.

C.-T. Huang, P.-C. Tseng, and L.-G. Chen, "Flipping structure: An efficient VLSI architecture for lifting-based discrete wavelet transform," IEEE Transactions on Signal Processing, vol. 52, no. 4, pp1080-1089, April 2004.

Books and Book Chapters

M. Tikekar, C.-T. Huang, C. Juvekar, V. Sze, and A. Chandrakasan, "Decoder Hardware Architecture for HEVC," included in High Efficiency Video Coding (HEVC): Algorithms and Architectures, editors V. Sze, M. Budagavi, G. J. Sullivan, Springer, 2014.
L.-G. Chen, C.-T. Huang, C.-Y. Chen, and C.-C. Cheng, "VLSI Design of Wavelet Transform: Analysis, Architecture, and Design Examples", Imperial College Press, 2006.

Conference Papers

H.-J. Tu, Y.-F. Ou, Y.-T. Chen, and C.-T. Huang, "A Biased Mixed-Precision Convolution Engine for Hardware-Efficient Computational Imaging CNN," in Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC), 2023.

K.-P. Lin, J.-H. Liu, J.-Y. Wu, H.-C. Liao, and C.-T. Huang, "VISTA: A 704mW 4K-UHD CNN Processor for Video and Image Spatial/Temporal Interpolation Acceleration," in IEEE International Solid-State Circuits Conference (ISSCC), 2023.

Y.-C. Ding, K.-P. Lin, C.-W. Weng, L.-W. Wang, H.-C. Wang, C.-Y. Lin, Y.-T. Chen, and C.-T. Huang, "A 4.6-8.3 TOPS/W 1.2-4.9 TOPS CNN-based Computational Imaging Processor with Overlapped Stripe Inference Achieving 4K Ultra-HD 30fps," in European Solid-State Circuits Conference (ESSCIRC), 2022.

Y.-T. Chen, Y.-F. Ou, and C.-T. Huang, "A Winograd-Based Highly-Parallel Convolution Engine for 8-bit CNN Acceleration," in IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022.

L.-Q. Weng, L.-D. Chen, H.-C. Cheng, A.-Y. Zheng, K.-P. Lin, and C.-T. Huang, "A HD 31fps 7x7-View Light-Field Factorization Processor for Dual-Layer 3D Factored Display", in IEEE International Solid-State Circuits Conference (ISSCC), 2022. [web]

H.-P. Hsu and C.-T. Huang, "Globally Assisted Instance Normalization for Bandwidth-Efficient Neural Style Transfer," in IEEE International Workshop on Signal Processing Systems (SiPS), 2021.

C.-T. Huang, "RingCNN: Exploiting Algebraically-Sparse Ring Tensors for Energy-Efficient CNN-Based Computational Imaging," in ACM/IEEE International Symposium on Computer Architecture (ISCA), 2021. [web]

C.-W. Weng and C.-T. Huang, "A Quality-Oriented Reconfigurable Convolution Engine Using Cross-Shaped Sparse Kernels for Highly-Parallel CNN Acceleration", in IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021.

C.-T. Huang, "ERNet: Hardware-Oriented CNN Models for Computational Imaging Using Block-Based Inference," in IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2020. [arXiv]

S.-Y. Huang, W.-C. Chen, and C.-T. Huang, "FIR Filter Design and Implementation for Phase-Based Processing," in IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2020.

C.-C. Wang, C.-T. Chiu, C.-T. Huang, Y.-C. Ding, and L.-W. Wang, "Fast and Accurate Embedded DCNN for RGB-D Based Sign Language Recognition," in IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2020.

C.-T. Huang, Y.-C. Ding, H.-C. Wang, C.-W. Weng, K.-P. Lin, L.-W. Wang, and L.-D. Chen, "eCNN: A Block-Based and Highly-Parallel CNN Accelerator for Edge Inference," in IEEE/ACM International Symposium on Microarchitecture (MICRO), 2019. [web]

P.-H. Chen, S.-W. Yang, S.-Y. Huang, L.-D. Chen and C.-T. Huang, "A 250mW 5.4G-Novel-Pixel/s Photorealistic Refocusing Processor for Full-HD Five-Camera Applications," in IEEE Symposium on VLSI Circuits (VLSIC), 2019.

H.-C. Huang, Y.-C. Wang, W.-C. Chen, P.-Y. Lin, and C.-T. Huang, "System and VLSI Implementation of Phase-Based View Synthesis," in IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2019.

Y.-L. Tsai, C.-T. Huang, and S.-J. Liu, "Satellite Image De-blurring Processing," in Asian Conference on Remote Sensing (ACRS), 2018.

L.-D. Chen, Y.-T. Lu, Y.-L. Hiao, B.-H. Yang, W.-C. Chen, and C.-T. Huang, "A 95pJ/label Wide-Range Depth-Estimation Processor for Full-HD Light-Field Applications on FPGA," in IEEE Asian Solid-State Circuits Conference (ASSCC), 2018.

B.-H. Yang, L.-D. Chen, and C.-T. Huang, "A 320M Pixel/s VLSI Architecture Design of Weighted Mode Filter for 4K Ultra-HD Depth Upsampling," in IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2018.

C.-T. Huang, "Robust Pseudo Random Fields for Light-Field Stereo Matching," in IEEE International Conference on Computer Vision (ICCV), 2017. (oral presentation) [web]

L.-D. Chen, Y.-L. Hsiao, and C.-T. Huang, "VLSI Architecture Design of Weighted Mode Filter for Full-HD Depth Map Upsampling at 30fps," in IEEE International Symposium on Circuits and Systems, 2016.

L.-R. Huang, Y.-W. Wang, and C.-T. Huang, "Fast Realistic Block-Based Refocusing for Sparse Light Fields," in IEEE International Symposium on Circuits and Systems, 2016.

L.-D. Chen, J.-J. Yu, W.-H. Cheng, and C.-T. Huang, "Sub-pixel Disparity Estimation in Continuous Space," in IEEE International Conference on Consumer Electronics - Taiwan, 2015.

C.-T. Huang, "Bayesian Inference for Neighborhood Filters with Application in Denoising," in IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 2015.

C.-T. Huang, J. Chin, H.-H. Chen, Y.-W. Wang, and L.-G. Chen, "Fast Realistic Refocusing for Sparse Light Fields," in IEEE International Conference on Acoustics, Speech and Signal Processing, 2015.

H.-H. Chen, C.-T. Huang, S.-S. Wu, C.-L. Hung, T.-C. Ma, and L.-G. Chen, "A 1920x1080 30fps 611mW Five-View Depth-Estimation Processor for Light-field Applications," in IEEE International Solid-State Circuits Conference (ISSCC), 2015.

M. Tikekar, C.-T. Huang, V. Sze, and A. Chandrakasan, "Energy and area-efficient hardware implementation of HEVC inverse transform and dequantization," in IEEE International Conference on Image Processing, 2014.

C.-T. Huang, C. Juvekar, M. Tikekar, and A. Chandrakasan, "HEVC Interpolation filter architecture for  Quad Full HD Decoding," in IEEE Visual Communications and Image Processing Conference, Nov 2013.

C.-T. Huang, M. Tikekar, C. Juvekar, V. Sze, and A. Chandrakasan, "A 249Mpixel/s HEVC Video-Decoder Chip for Quad Full HD Applications," in IEEE International Solid-State Circuits Conference (ISSCC), pp. 162-163, Feb 2013.

C.-C. Cheng, C.-T. Huang, J.-Y. Chang, and L.-G. Chen, "Line Buffer Wordlength Analysis for Line-Based 2-D DWT," in IEEE International Conference on Acoustics, Speech, and Signal Processing, 2006, vol. 3.

C.-C. Cheng, P.-C. Tseng, C.-T. Huang, and L.-G. Chen, "Multi-mode Embedded Compression Codec Engine for Power-aware Video Coding System," in IEEE Workshop on Signal Processing Systems Design and Implementation, 2005, pp532-537.

C.-Y. Chen, C.-T. Huang, Y.-H. Chen, C.-J. Lian, and L.-G. Chen, "System Analysis of VLSI Architecture for Motion-Compensated Temporal Filtering," in IEEE International Conference on Image Processing, 2005, vol. 3, pp11-14.

C.-C. Cheng, C.-T. Huang, P.-C. Tseng, C.-H. Pan, and L.-G. Chen, "Multiple-lifting Scheme: Memory-efficient VLSI Implementation for Line-based 2-D DWT," in IEEE International Symposium on Circuits and Systems, 2005, vol. 5, pp5190-5193.

T.-C. Chen, Y.-W. Huang, C.-Y. Tsai, C.-T. Huang, and L.-G. Chen, "Single Reference Frame Multiple Current Macroblocks Scheme for Multi-frame Motion Estimation in H.264/AVC," in IEEE International Symposium on Circuits and Systems, 2005, vol. 2, pp1790-1793.

C.-T. Huang, C.-Y. Chen, Y.-H. Chen, and L.-G. Chen, "Memory Analysis of VLSI Architecture for 5/3 and 1/3 Motion-Compensated Temporal Filtering," in IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005, vol. 5, pp93-96.

C.-T. Huang, P.-C. Tseng, and L.-G. Chen, "Memory Analysis and Architecture for Two-Dimensional Discrete Wavelet Transform," in IEEE International Conference on Acoustics, Speech, and Signal Processing, 2004, vol. 5, pp13-16.

C.-T. Huang, P.-C. Tseng, and L.-G. Chen, "B-spline Factorization-Based Architecture for Inverse Discrete Wavelet Transform," in IEEE International Symposium on Circuits and Systems, 2004, vol. 2, pp829-833.

P.-C. Tseng, C.-T. Huang, and L.-G. Chen, "Reconfigurable Discrete Cosine Transform Processor for Object-Based Video Signal Processing," in IEEE International Symposium on Circuits and Systems, 2004, vol. 2, pp353-356.

H.-C. Fang, C.-T. Huang, Y.-W Chang, T.-C. Wang, P.-C. Tseng, C.-J. Lian, and L.-G. Chen, "81 MS/s JPEG 2000 Single-Chip Encoder with Rate-Distortion Optimization," in IEEE International Solid-State Circuits Conference (ISSCC), 2004.

C.-T. Huang, P.-C. Tseng, and L.-G. Chen, "VLSI Architecture for Discrete Wavelet Transform Based on B-spline Factorization," in IEEE Workshop on Signal Processing Systems, 2003, pp346-350.

P.-C. Tseng, C.-T. Huang, and L.-G. Chen, "Reconfigurable Discrete Wavelet Transform Architecture for Advanced Multimedia Systems," in IEEE Workshop on Signal Processing Systems, 2003, pp137-141.

C.-T. Huang, P.-C. Tseng, and L.-G. Chen, "Hardware Implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank," in IEEE International Conference on Image Processing, 2003, vol. 2, pp571-574.

C.-T. Huang, P.-C. Tseng, and L.-G. Chen, "Flipping structure: An efficient VLSI architecture for lifting-based discrete wavelet transform," in Asia-Pacific Conference on Circuits and Systems, 2002, pp. 383-388.

P.-C. Tseng, C.-T. Huang, and L.-G. Chen, "Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method," in Asia-Pacific Conference on Circuits and Systems, 2002, pp. 363-366.

C.-T. Huang, P.-C. Tseng, and L.-G. Chen, "Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method," in IEEE International Symposium on Circuits and Systems, 2002, vol. 5, pp. 565-568.
P.-C. Wu, C.-T. Huang, and L.-G. Chen, "An efficient architecture for two-dimensional inverse discrete wavelet transform," in IEEE International Symposium on Circuits and Systems, 2002, vol. 2, pp. 312-315.

P.-C. Tseng, C.-T. Huang, and L.-G. Chen, "VLSI implementation of shape-adaptive discrete wavelet transform," in Proc. of SPIE International Conference on Visual Communications and Image Processing, 2002, pp. 655-666.

US Patent

C.-T. Huang, "Block-based digital refocusing system and method thereof," US Patent 9,531,943.

C.-T. Huang and J. Chin, "Digital refocusing method," US Patent 9,497,437.

Y.-J. Huang, C.-T. Huang, and T.-S. Huang, "Apparatus for reference picture resampling generation and method thereof and video decoding system using the same," US Patent 8,644,381, 2014/2/4.

Y.-C. Chen, C.-T. Huang, Y.-W. Chang, "Intra prediction mode selecting apparatus and method thereof," US Patent 8,411,747, 2013/4/2.

Y.-H. Lu and C.-T. Huang, "Adaptive canonical Huffman decoder and method thereof and video decoder," US Patent 8,306,108, 2012/11/6.

C.-T. Huang and Y.-W. Chang, "Bit rate control circuit and method for image compression," US Patent 8,300,967, 2012/10/30.

C.-T. Huang, "Operation method and apparatus for performing overlap filter and core transform," US Patent 8,285,774, 2012/10/9.

C.-T. Huang, and C.-P. Lin, "Method and apparatus for generating coded block pattern for highpass coefficients," US Patent 8,233,729, 2012/7/31.

C.-T. Huang, "Method and apparatus for cost calculation in decimal motion estimation," US Patent 7,974,481, 2011/7/5.

C.-T. Huang and P.-C. Tseng, "Method and apparatus for motion estimation," US Patent 7,949,194, 2011/5/24.

C.-T. Huang and P.-C. Tseng, "Apparatus and method for motion estimation supporting multiple video compression standards," US Patent 7,782,952, 2010/8/24.

L.-G. Chen, C.-T. Huang, and P.-C. Tseng, "Flipping algorithm to architectures of hardware realization for lifting-based DWT," US Patent 7,076,515, 2006/06/11.