Publications

Publication Record

Publications are presented as searchable text, grouped by venue type and ordered by publication date from newest to oldest.

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International Journals (63)

[1]
Jen-Chun Tien, Ping-Chun Wu, Win-San Khwa, Ashwin Sanjay Lele, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Meng-Fan Chang , “A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device,” IEEE Journal of Solid-State Circuits, vol 61, no. 1, pp.211-224, Jan . 2026 ..
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[2]
John Carl Joel S. Marquez, Hsin Yu, Chih-Cheng Hsieh , “A 15-bit ROIC with Current Mode Folding Integration Technique for Microbolometer Thermal Imagers,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol 34, no. 2, pp.332-342, Feb . 2026 .
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[3]
De-Qi You, Win-San Khwa, Bo Zhang, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Yi-Ming Li, Yu-Hui Wang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang , “A μ-NMC-Δ-IMC Heterogeneous STT-MRAM Compute-in-Memory Macro Using Δ-Clamping Bit Reduction for Noise-Tolerant Bayesian Neural Networks,” IEEE Journal of Solid-State Circuits, vol 61, no. 1, pp.225-236, Jan . 2026 .
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[4]
Ping-Chun Wu, Win-San Khwa, Jui-Jen Wu, Jian-Wei Su, Chuan-Jia Jhang, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Meng-Fan Chang , “An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips,” IEEE Journal of Solid-State Circuits, vol 60, no. 1, pp.158-170, Jan . 2025 .
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[5]
Hung-Hsi Hsu, Tai-Hao Wen, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Ashwin Sanjay Lele, Bo Zhang, Ping-Sheng Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Shih-Hsin Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang , “A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device,” IEEE Journal of Solid-State Circuits, vol 60, no. 1, pp.171-183, Jan . 2025 .
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[6]
Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Meng-Fan Chang , “An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips,” IEEE Journal of Solid-State Circuits, vol 59, no. 7, pp.2297-2309, July . 2024 .
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[7]
Jian-Wei Su, Pei-Jung Lu, Ping-Chun Wu, Yen-Chi Chou, Ta-Wei Liu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Hao-Chiao Hong, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Meng-Fan Chang , “8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol 71, no. 4 . pp. 2304-2308 Apr. 2024.
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[8]
Tai-Hao Wen, Je-Min Hung, Wei-Hsing Huang, Chuan-Jia Jhang, Yun-Chen Lo, Hung-Hsi Hsu, Zhao-En Ke, Yu-Chiao Chen, Yu-Hsiang Chin, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Meng-Fan Chang , “Fusion of memristor and digital compute-in-memory processing for energy-efficient edge computing,” Science, vol. 384, issue 6693, pp.325-332, Apr. 2024.
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[9]
De-Qi You, Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang , “An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices,” IEEE Journal of Solid-State Circuits, vol 59, no. 1, pp.219-230, Jan . 2024 .
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[10]
Hung-Hsi Hsu, Tai-Hao Wen, Wei-Hsing Huang, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Yu-Hsiang Chin, Yu-Chiao Chen;, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh , Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang , “A Nonvolatile AI-Edge Processor With SLC–MLC Hybrid ReRAM Compute-in-Memory Macro Using Current–Voltage-Hybrid Readout Scheme,” IEEE Journal of Solid-State Circuits, vol 59, no. 1, pp.116-127, Jan. 2024 .
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[11]
Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Meng-Fan Chang , “A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips,” IEEE Journal of Solid-State Circuits, vol 59, no. 1, pp.196-207, Jan. 2024 .
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[12]
Tzu-Hsiang Hsu, Guan-Cheng Chen, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, and Chih-Cheng Hsieh, “A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification,” IEEE Journal of Solid-State Circuits, vol 58, no. 11, pp. 3266-3274, Nov . 2023 .
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[13]
Min-Yang Chiu, Guan-Cheng Chen, Tzu-Hsiang Hsu, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, and Chih-Cheng Hsieh, “A Multi-Mode Vision Sensor with Temporal Contrast Pixel and Column-Parallel Local Binary Pattern Extraction for Dynamic Depth Sensing Using Stereo Vision,” IEEE Journal of Solid-State Circuits, vol 58, no. 10, pp. 2767-2777, Oct . 2023 .
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[14]
Chih-Cheng Chen, Yu-Hsiang Huang, John Carl Joel S. Marquez, and Chih-Cheng Hsieh, “A 12-ENOB Second-Order Noise Shaping SAR ADC with PVT-insensitive Voltage-Time-Voltage Converter,” IEEE Journal of Solid-State Circuits, vol 58, no. 10, pp. 2897-2906, Oct . 2023 .
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[15]
Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Tianlong Pan, Chuan-Jia Jhang, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Meng-Fan Chang , "A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips," IEEE Journal of Solid-State Circuits, vol 58, no. 3, pp. 877-892, Mar . 2023.
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[16]
Je-Min Hung, Tai-Hao Wen, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang , "8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices," IEEE Journal of Solid-State Circuits, vol 58, no. 1, pp. 303-315, Jan . 2023.
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[17]
Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Yen-Lin Chung, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Hongwu Jiang, Shanshi Huang, Sih-Han Li, Shyh-Shyuan Sheu, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Shimeng Yu, Meng-Fan Chang , "Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips," IEEE Journal of Solid-State Circuits, vol 57, no. 2, pp. 609-624, Feb. 2022.
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[18]
Syuan-Hao Sie, Jye-Luen Lee, Yi-Ren Chen, Zuo-wei Yeh, Zhaofang Li, Chih-Cheng Lu, Chih-Cheng Hsieh , Meng-Fan Chang, Kea-Tiong Tang , "MARS: Multi-macro Architecture SRAM CIM-Based Accelerator with Co-designed Compressed Neural Networks," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol 41, no. 5, pp. 1550-1562, May. 2022.
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[19]
Je-Min Hung, Cheng-Xin Xue, Hui-Yao Kao, Yen-Hsiang Huang, Fu-Chun Chang, Sheng-Po Huang, Ta-Wei Liu, Chuan-Jia Jhang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Mon-Shu Ho, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chan g, “A four-megabit compute-in-memory macro with eight-bit precision based on CMOS and resistive random-access memory for AI edge devices,” Nature Electronics , vol 4, pp. 921-930, Dec. 2021
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[20]
Xin Si , Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su, Pei-Jung Lu, Jing-Hong Wang, Ta-Wei Liu, Ssu-Yen Wu, Ruhui Liu, Yen-Chi Chou, Yen-Lin Chung, William Shih, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Nan-Chun Lien, Wei-Chiang Shih, Yajuan He, Qiang Li, Meng-Fan Chang , “A Local Computing Cell and 6T SRAM based Computing-in-Memory Macro with 8b MAC Operation for Edge AI Chips,” IEEE Journal of Solid-State Circuits, vol 56, no. 9, pp. 2817-2831, Sep. 2021.
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[21]
Tzu-Hsiang Hsu, Yen-Kai Chen, Min-Yang Chiu, Guan-Cheng Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, and Chih-Cheng Hsieh, “A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel,” IEEE Journal of Solid-State Circuits, vol 56, no. 8, pp. 2516-2524, Aug. 2021.
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[22]
Tzu-Hsiang Hsu, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh , "A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Feature Extraction," IEEE Journal of Solid-State Circuits, v ol 56, no. 5, pp. 1588-1596, May. 2021.
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[23]
Cheng-Xin Xue, Yen-Cheng Chiu, Ta-Wei Liu, Tsung-Yuan Huang, Je-Syu Liu, Ting-Wei Chang, Hui-Yao Kao, Jing-Hong Wang, Shih-Ying Wei, Chun-Ying Lee, Sheng-Po Huang, Je-Min Hung, Shih-Hsih Teng, Wei-Chen Wei, Yi-Ren Chen, Tzu-Hsiang Hsu, Yen-Kai Chen, Yun-Chen Lo, Tai-Hsing Wen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Mon-Shu Ho, Meng-Fan Chang, “A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices”, Nature Electronics , vol 4, pp. 81-90, Dec. 2020.
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[24]
Yen-Cheng Chiu, Zhixiao Zhang, Jia-Jing Chen, Xin Si, Ruhui Liu, Yung-Ning Tu, Jian-Wei Su, Wei-Hsing Huang, Jing-Hong Wang, Wei-Chen Wei, Je-Min Hung, Shyh-Shyuan Sheu, Sih-Han Li, Chih-I Wu, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Meng-Fan Chang , “A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors,” IEEE Journal of Solid-State Circuits, vol 55, no. 10, pp. 2790-2801, Oct. 2020.
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[25]
Cheng-Xin Xue, Wei-Hao Chen, Je-Syu Liu, Jia-Fang Li, Wei-Yu Lin, Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Tsung-Yuan Huang, Ting-Wei Chang, Tung-Cheng Chang, Hui-Yao Kao, Yen-Cheng Chiu, Chun-Ying Lee, Ya-Chin King, Chrong-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Meng-Fan Chang , "Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors," IEEE Journal of Solid-State Circuits, vol 55, no. 1, pp. 203-215, Jan. 2020.
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[26]
Xin Si, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Qiang Li, Meng-Fan Chang , “A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors,” IEEE Journal of Solid-State Circuits, vol 55, no. 1, pp. 189-202, Jan. 2020.
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[27]
Kwuang-Han Chang and Chih-Cheng Hsieh , "A Calibration-Free 13-bit 10-MS/s Full-Analog SAR ADC With Continuous-Time Feedforward Cascaded (CTFC) Op-Amps," IEEE Journal of Solid-State Circuits, vol 54, no. 10, pp. 2691-2702, Oct. 2019.
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[28]
Wei-Hao Chen, Chunmeng Dou, Kai-Xiang Li, Wei-Yu Lin, Pin-Yi Li, Jian-Hao Huang, Jing-Hong Wang, Wei-Chen Wei, Cheng-Xin Xue, Yen-Cheng Chiu, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, J. Joshua Yang, Mon-Shu Ho, Meng-Fan Chang , CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors, Nature Electronics , vol. 2, pp. 420-428, Aug. 2019.
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[29]
Kwuang-Han Chang and Chih-Cheng Hsieh , "A Calibration-Free 12-bit 50-MS/s Full-Analog SAR ADC With Feedback Zero-Crossing Detectors," IEEE Journal of Solid-State Circuits, vol 54, no. 6, pp. 1624-1635, June. 2019.
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[30]
Sung-En Hsieh, and Chih-Cheng Hsieh , "A 0.4 V 13-bit 270 kS/s SAR-ISDM ADC with Opamp-Less Time-Domain Integrator," IEEE Journal of Solid-State Circuits, vol 54, no. 6, pp. 1648-1686, June. 2019.
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[31]
Albert Yen-Chih Chiou, and Chih-Cheng Hsieh , "An ULV PWM CMOS Imager with Adaptive-Multiple-Sampling Linear Response, HDR Imaging, and Energy Harvesting," IEEE Journal of Solid-State Circuits, vol 54, no. 1, pp. 298-306, Jan. 2019.
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[32]
Sung-En Hsieh, Chen-Che Kao, and Chih-Cheng Hsieh , "A 0.5V 12-bit SAR ADC using Adaptive Time-Domain Comparator with Noise Optimization," IEEE Journal of Solid-State Circuits, vol 53, no. 10, pp. 2763-2771, Oct. 2018.
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[33]
Ting-I Chou, Kwuang-Han Chang, Jia-Yin Jhang, Shih-Wen Chiu, Guoxing Wang, Chia-Hsiang Yang, Herming Chiueh, Hsin Chen, Chih-Cheng Hsieh , Meng-Fan Chang, Kea-Tiong Tang*, A 1V 2.6mW Environmental Compensated Fully Integrated Nose-on-a-Chip, IEEE Transaction on Circuits and Systems II: Express Briefs (TCAS-II) , vol. 65, no. 10, pp.1365-1369, Oct 2018.
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[34]
Tzu-Hsiang Hsu, Ting Liao, Nien- An Lee, and Chih-Cheng Hsieh , "A CMOS Time-of-Flight Depth Image Sensor With In-Pixel Background Light Cancellation and Phase Shifting Readout Technique," IEEE Journal of Solid-State Circuits, vol 53, no. 10, pp. 2898-2905, Oct. 2018.
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[35]
Sung-En Hsieh and Chih-Cheng Hsieh , "A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC," IEEE Journal of Solid-State Circuits, vol 53, no. 9, pp. 2595-2603, Sept. 2018.
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[36]
Kwuang-Han Chang and Chih-Cheng Hsieh , "A 12-bit 150-MS/s Sub-Radix-3 SAR ADC with Switching Miller Capacitance Reduction," IEEE Journal of Solid-State Circuits , vol 53, no. 6, pp. 1755-1764, June. 2018.
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[37]
Kwuang-Han Chang and Chih-Cheng Hsieh , "A Hybrid Analog-to-Digital Conversion Algorithm with Sub-radix and Multiple Quantization Thresholds," IEEE Transaction on Circuits and Systems I , vol. 64, no. 6, pp. 1400-1408, June. 2017.
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[38]
Chin Yin, Kuan-Lin Liu, Chin-Fong Chiu, and and Chih-Cheng Hsieh , " A 32-stage 15-bit Digital Time Delay Integration Linear CMOS Image Sensor with Data Prediction Switching Technique," IEEE Transaction on Electron Devices, vol. 64, no. 3, pp. 1167-1173, Mar. 2017 .
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[39]
Jin-Yi Lin and Chih-Cheng Hsieh , " A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90 nm CMOS," IEEE Transaction on Circuits and Systems I, vol. 64, no. 3, pp. 562-572, Mar. 2017 .
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[40]
Pei-Chen Lee, Jin-Yi Lin, and Chih-Cheng Hsieh , " A 0.4 V 1.94 fJ/conversion-step 10-bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching," IEEE Transaction on Circuits and Systems I, vol. 63, no. 12, pp. 2149-2157, Dec. 2016 .
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[41]
Sung-En Hsieh and Chih-Cheng Hsieh , " A 0.3V 0.705fJ/Conversion-step 10-bit SAR ADC with Shifted Monotonic Switching Procedure in 90nm CMOS," IEEE Transaction on Circuits and Systems II, vol. 63, no. 12, pp. 1171-1175, Dec. 2016 .
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[42]
Albert Yen-Chih Chiou and Chih-Cheng Hsieh , " A 137dB Dynamic Range and 0.32V Self-Powered CMOS Imager with Energy Harvesting Pixels," IEEE Journal of Solid-State Circuits , vol 51, no. 11, pp. 2769-2776, Nov. 2016.
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[43]
Pei-Yi Lai Lee, Chih-Wen Lu, Chih-Cheng Hsieh , Tsin-Yuan Chang, Jenny Yi-Chun Liu, Hsin-Chin Liang, Hsiang-Ning Wu, Electric Hum Signal Readout Circuit for Touch Screen Panel Applications, Journal of Display Technology, vol. 12, no. 11, pp. 1444-145, Nov. 2016.
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[44]
Chin Yin, Chin-Fong Chiu, and Chih-Cheng Hsieh , " A 0.5 V, 14.28 kfps, 109 dB Smart Image Sensor With Array-Level Image Signal Processing for IoT Applications," IEEE Transaction on Electron Devices, vol. 63, no. 3, pp. 1134-1140, Mar. 2016 .
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[45]
Yan-Jiun Chen, Kwuang-Han Chang, and Chih-Cheng Hsieh , "A 2.02V5.16 fJ/Conversion-step 10-Bit Hybrid Coarse-Fine SAR ADC With Time-domain Quantizer in 90-nm CMOS," IEEE Journal of Solid-State Circuits , vol. 51, no. 2, pp. 357-364, Feb. 2016 .
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[46]
Chih-Lin Lee, and Chih-Cheng Hsieh , A 0.5 V/1.8 V High Dynamic Range CMOS Imager for Artificial Retina Applications, IEEE Sensors Journal, vol. 15, no. 12, pp. 1625-1632, Dec. 2015 .
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[47]
Jin-Yi Lin and Chih-Cheng Hsieh , A 0.3V 10-bit 1.17f SAR ADC with Merge and Split Switching in 90nm CMOS , IEEE Transaction on Circuits and Systems I , vol. 62, no. 1, pp. 70-79, Jan. 2015 .
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[48]
Shih-Wen Chiu, Jen-Huo Wang, Kwuang-Han Chang, Ting-Hau Chang, Chia-Min Wang, Chia-Lin Chang, Chen-Ting Tang, Chien-Fu Chen, Chung-Hung Shih, Han-Wen Kuo, Li-Chun Wang, Hsin Chen, Chih-Cheng Hsieh , Meng-Fan Chang, Yi-Wen Liu, Tsan-Jieh Chen, Chia-Hsiang Yang, Herming Chiueh, Juyo-Min Shyu, Kea-Tong Tang, A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia , IEEE Transaction on Biomedical Circuits and Systems , vol. 8, no. 6, pp. 765-778, Dec. 2014 .
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[49]
Wei-Fan Chou, Shang-Fu Yeh, Chin-Fong Chiu, and Chih-Cheng Hsieh , A Linear-Logarithmic CMOS Image Sensor with Pixel-FPN Reduction and Tunable Response Curve, IEEE Sensors Journal , vol. 14, no. 5, pp. 1625-1632, May 2014 .
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[50]
Shang-Fu Yeh, and Chih-Cheng Hsieh , A Novel Single Slope ADC Design for Full Well Capacity Expansion of CMOS Image Sensor, IEEE Sensors Journal, vol. 13, no. 3, pp. 1012-1017, Mar. 2013 .
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[51]
Meng-Ting Chung, Chih-Lin Lee, Chin Yin, and Chih-Cheng Hsieh , A 0.5 V PWM CMOS Imager with 82 dB Dynamic Range and 0.055% Fixed-Pattern-Noise, IEEE Journal of Solid-State Circuits , vol. 48, no. 10, pp. 2522-2530, Oct. 2013 .
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[52]
Chi-Ying Lee, Chih-Cheng Hsieh , and Jenn-Chyou Bor, A 2.4-GHz 10-Mbps BFSK Embedded Transmitter With a Stacked-LC DCO for Wireless Testing Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol. 21, no. 9, pp. 1727-1737, Sep. 2013
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[53]
Shang-Fu Yeh, and Chih-Cheng Hsieh , and Ka-Yi Yeh, A 3 megapixel 100Fps 2.8gm Pixel Pitch CMOS Image Sensor Layer with Built-in Self-test for 3D Integrated Imagers, IEEE Journal of Solid-State Circuits , vol. 48, no. 3, pp. 839-849, Mar. 2013 .
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[54]
Chih-Lin Lee, and Chih-Cheng Hsieh , A 0.8V 4096 Pixels CMOS Sense-and-Stimulus Imager for Retinal Prosthesis, IEEE Transaction on Electron Devices, vol. 60, no. 3, pp. 1162-1168, Mar. 2013 .
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[55]
Wei-Lin Chen, and Chih-Cheng Hsieh , Exploration of Second-Order Effects in High-Performance Continuous-Time UG Modulators Using Discrete-Time Models, IEEE Transaction on Circuits and Systems I, vol. 59, no. 12, pp. 2890-2900, Dec. 2012 .
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[56]
Tsan-Jieh Chen, Herming Chiueh , Chih-Cheng Hsieh *, Chin Yin, Wen-Hsu Chang, Hann-Huei Tsai, and Chin-Fong Chiu, A High Definition Image Pre-Processing System for Multi-Stripe Satellites Image Sensors, IEEE Sensors Journal , vol. 12, no. 9, pp. 2859-2865, Sep. 2012 .
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[57]
Shang-Fu Yeh, Chih-Cheng Hsieh , Chiao-Jen Cheng, and Chun-Kai Liu, A Dual-Exposure Single-Capture Wide Dynamic Range CMOS Image Sensor with Column-Wise Highly/Lowly-Illuminated Pixel Detection, IEEE Transaction on Electron Devices, vol. 59, no. 7, pp. 1948-1955, July 2012 .
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[58]
Kea-Tiong Tang , Shih-Wen Chiu, Meng-Fan Chang*, Chih-Cheng Hsieh *, and Juyo-Min Shyu*, A Low-Power Electronic Nose Signal Processing Chip for a Portable Artificial Olfaction System, IEEE Transaction on Biomedical Circuits and Systems , vol. 5, no. 4, pp. 380-390, Aug. 2011.
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[59]
Chung-Yu Wu*; Yu-Chuan Shih; Jeng-Feng Lan; Chih-Cheng Hsieh ; Chien- Chang Huang; Jr-Houng Lu; Design, Optimization, and Performance Analysis of New Photodiode Structures for CMOS Active-Pixel-Sensor (APS) Imager Applications, IEEE Sensor Journal , vol. 4, no. 1, pp. 135-144, Feb. 2004.
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[60]
Chih-Cheng Hsieh , Chung-Yu Wu*, Tai-Ping Sun, Far-Wen Jih; and Ya-Tung Cherng, High-performance CMOS buffered gate modulation input (BGMI) readout circuits for IR FPA, IEEE Journal of Solid-State Circuits , vol. 33, no. 8, pp. 1188-1198, Aug. 1998.
IEEE Xplore ↗
[61]
Chih-Cheng Hsieh , Chung-Yu Wu* and Tai-Ping Sun, A New Cryogenic CMOS Readout Structure for Infrared Focal Plane Array, IEEE Journal of Solid-State Circuits , vol. 32, no. 8, pp. 1192-1199, Aug. 1997.
IEEE Xplore ↗
[62]
Chih-Cheng Hsieh , Chung-Yu Wu*, Far-Wen Jih and Tai-Ping Sun, Focal-Plane-Arrays and CMOS Readout Techniques of Infrared Imaging Systems, IEEE Trans. on Circuits and Systems for Video Technology , vol. 7, no. 4, pp. 594-605, Aug. 1997.
IEEE Xplore ↗
[63]
Chung-Yu Wu* and Chih-Cheng Hsieh , New Design Techniques for a Complementary Metal-Oxide Semiconductor Current Readout Integration Circuit for Infrared Detector arrays, Optical Engineering , vol. 34, no. 1, pp. 160-168, Jan. 1995.
IEEE Xplore ↗

International Conferences (100)

[1]
H-H. Hsu, W-S. Khwa, Y-K. Yeh, C-L. Wu, C-Y. Chen, Y-C. Huang, Y-H. Lin, C-F. Chang, Y-T. Shao, J-C. Tien, D-Q. You, P-S. Wu, B. Zhang, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, M-F. Chang , A 22nm 96Mb 50.6-to-90.2TFLOPS/W Non-Linear MLC ReRAM CIM Macro with High-Retention for Mamba/Transformer/CNN, 2026 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2026.
IEEE Xplore ↗
[2]
J-C. Tien, W-S. Khwa, L-J. Hsieh, T-H. Lou, J-C. Bai, Y-S. Kao, T-H. Hsu, M. Tseng, H-H. Hsu, Y-K. Yeh, D-Q. You, A. S. Lele, B. Crafton, B. Zhang, P-S. Wu2, Y-T. Yang, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, M-F. Chang , A 16nm 72kb 120.5TFLOPS/W Versatile-Format Dual-Representation Gain-Cell CIM Macro for General Purpose AI Tasks, 2026 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2026.
IEEE Xplore ↗
[3]
Y-K. Yeh, J-W. Su, T-H. Hsu, M. Tseng, J-C. Tien, K-C. Chen, C-Y. Yue, Y-E. Lin, Y-J. Hu, L-J. Hsieh, J-C. Bai, Y-S. Kao, T-H. Lou, H-H. Hsu, D-Q. You, S. Shyh-Shyuan, W-C. Lo, S-C. Chang, Y-T. Yang, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, M-F. Chang , A 16nm, 1Mb, 1-to-8b-Configurable 444.21TOPS/W Fully Digital SRAM Compute-In-Memory Macro for Hybrid SNN-CNN Edge Computing, 2026 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2026.
IEEE Xplore ↗
[4]
Po-Hsi Lee, Yu-Hsiang Huang, Chih-Cheng Hsieh , A 435 KS/s 10-bit Column-Parallel Hybrid ADC Using Range-Partitioned Quantization with Asynchronous Charge-Injection and Single-Slope Conversion, 2025 IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2025.
IEEE Xplore ↗
[5]
Liang-Yu Huang, Guan-Cheng Chen, Chung-Chuan Lo, Ren-Shuo Liu, Min Sun, Meng-Fan Chang, Kea-Tiong Tang, Chih-Cheng Hsieh , A 128×128 Dual-Resolution CMOS Image Sensor with In-Sensor Temporal and Spatial Gradient Calculations for Optical Flow Pre-Processing, 2025 IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2025.
IEEE Xplore ↗
[6]
Chun-Yi Wu, Ssu-Lei Tu, Chih-Cheng Hsieh , A 32×32 120.4dB Self-Calibrated Analog Counters with Extrapolation for SPAD Imager, 2025 IEEE Sensors Conference , Oct. 2025.
IEEE Xplore ↗
[7]
Cheng-Jhe Li, Guan-Cheng Chen, Chih-Cheng Hsieh , A Digital Pixel Sensor with 0.17%/-0.32% Non- Linearity and 75.3μW Power Consumption Using Wide-Swing PWM and Embedded 10-bit 3T-GC-eDRAM, 2025 International Image Sensor Workshop (IISW) , June. 2025.
IEEE Xplore ↗
[8]
D-Q. You, W-S. Khwa, B. Zhang, F-Y. Chen, A. Lee1, Y-C. Hung, Y-M. Li, Y-H. Wang, C-C. Lo, R-S. Liu, K-T. Tang, Chih-Cheng Hsieh, Y-D. Chih, T-Y. J. Chang, M-F. Chang , A 22nm 104.5TOPS/W μ-NMC-Δ-IMC Heterogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Networks, 2025 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2025.
IEEE Xplore ↗
[9]
Yu-Tang Shen, John Carl Joel Marquez, Chih-Cheng Hsieh , A nMOS-Only Pulse-Width Modulation CMOS Imager with Body Effect Mitigation Using Differential Comparison Technique, in 2024 IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2024.
IEEE Xplore ↗
[10]
[Invited Talk] Chih-Cheng Hsieh , Intelligent Imager with Processing-in-Sensor Techniques, International Workshop on Image Sensors and Imaging Systems (IWISS) , Nov. 2024.
IEEE Xplore ↗
[11]
De-Qi You, Win-San Khwa, Jui-Jen Wu, Chuan-Jia Jhang, Guan-Yi Lin, Po-Jung Chen, Ting-Chien Chiu, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang , A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro, 2024 Symposium on VLSI Technology and Circuits (VLSI Symposium) , June. 2024.
IEEE Xplore ↗
[12]
Pao-Shu Liu, Yu-Hsiang Huang, Chih-Cheng Hsieh , A Low-OSR 5th-Order Noise Shaping SAR ADC Using EF-EF-CIFF Structure with PVT-Robust Differential V-T-V Converter, 2024 Symposium on VLSI Technology and Circuits (VLSI Symposium) , June. 2024.
IEEE Xplore ↗
[13]
[Invited Forum Talk] Chih-Cheng Hsieh , Intelligent Imager with Processing-in-Sensor Techniques, IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2024.
IEEE Xplore ↗
[14]
W-S. Khwa, P-C. Wu, J-J. Wu, J-W. Su, H-Y. Chen, Z-E. Ke, T-C. Chiu, J-M. Hsu, C-Y. Cheng, Y-C. Chen, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh , K-T. Tang, M-F. Chang , A 16nm 96Kb Integer-Floating-Point Dual-Mode Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices, 2024 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2024.
IEEE Xplore ↗
[15]
T-H. Wen, H-H. Hsu, W-S. Khwa, W-H. Huang, Z-E. Ke, Y-H. Chin, H-J. Wen, Y-C. Chang, W-T. Hsu, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh , K-T. Tang, S-H. Teng, C-C. Chou, Y-D. Chih, T-Y. J. Chang, M-F. Chang , A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices, 2024 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2024.
IEEE Xplore ↗
[16]
Hsin Yu, John Carl Joel Salao Marquez, Chih-Cheng Hsieh , A -20 o C~+107 o C 52mk-NETD Reference-cell-free 15-bits ROIC for 80x60 Microbolometer Thermal Imager, 2023 Symposium on VLSI Technology and Circuits (VLSI Symposium) , June. 2023.
IEEE Xplore ↗
[17]
Tai-Hao Wen, Je-Min Hung, Hung-Hsi Hsu, Yuan Wu, Fu-Chun Chang, Chung-Yuan Li, Chih-Han Chien, Chin-I Su, Win-San Khwa, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh , Kea-Tiong Tang, Mon-Shu Ho, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang , A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices, 2023 Symposium on VLSI Technology and Circuits (VLSI Symposium) , June. 2023.
IEEE Xplore ↗
[18]
Yu-Hsiang Huang, Min-Ruei Wu, Chih-Cheng Hsieh , A CMOS Image Sensor With 1.6us Conversion Time 10-bits Column-Parallel Hybrid ADC Using Self-Adaptive Charge-Injection Cell, 2023 International Image Sensor Workshop (IISW) , May. 2023.
IEEE Xplore ↗
[19]
P-C. Wu, J-W. Su, L-Y. Hong, J-S. Ren, C-H. Chien, H-Y. Chen, C-E. Ke, H-M. Hsiao, S-H. Li, S-S. Sheu, W-C. Lo, S-C. Chang, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh , K-T. Tang, M-F. Chang , A 22-nm 832-kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices, 2023 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2023.
IEEE Xplore ↗
[20]
W-H. Huang, T-H. Wen, J-M. Hung, W-S. Khwa, Y-C. Lo, C-J. Jhang, H-H. Hsu, Y-H. Chin, Y-C. Chen, C-C. Lo, R-S. Liu, K-T. Tang, Chih-Cheng Hsieh , Y-D. Chih, T-Y. Chang, M-F. Chang , A Nonvolatile AI-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W, 2023 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2023.
IEEE Xplore ↗
[21]
Y-C. Chiu, W-S. Khwa, C-Y. Li, F-L. Hsieh, Y-A. Chien, G-Y. Lin, P-J. Chen, T-H. Pan, D-Q. You, F-Y. Chen, A. Lee, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh , K-T. Tang, Y-D. Chih, T-Y. Chang, M-F. Chang , A 22-nm 8-Mb 46.4-160.1-TOPS/W STT-MRAM Near-Memory-Computing Macro with 8b precision for AI-edge Devices, 2023 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2023.
IEEE Xplore ↗
[22]
Y-C. Chiu, W-S. Khwa, C-S. Yang, S-H. Teng, H-Y. Huang, F-C. Chang, Y. Wu, Y-A. Chien, F-L. Hsieh, C-Y. Li, G-Y. Lin, P-J. Chen, T-H. Pan, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh , K-T. Tang, C-P. Lo, Y-D. Chih, T-Y. J. Chang, M-F. Chang , A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read- and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations, 2022 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2022.
IEEE Xplore ↗
[23]
Min-Yang Chiu, Guan-Cheng Chen, Yu-Hsiang Huang, Tzu-Hsiang Hsu, Chung-Chuan Lo, Ren-Shuo Liu, Meng-Fan Chang, Kea-Tiong Tang, Chih-Cheng Hsieh , A 0.56V/0.8V Vision Sensor with Temporal Contrast Pixel and Column-Parallel Local Binary Pattern Extraction for Dynamic Depth Sensing Using Stereo Vision, in 2022 IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2022.
IEEE Xplore ↗
[24]
T-H. Hsu, G-C. Chen, Y-R. Chen, C-C. Lo, R-S. Liu, M-F. Chang, K-T. Tang, Chih-Cheng Hsieh , A 0.8V Intelligent Vision Sensor with Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification, 2022 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2022.
IEEE Xplore ↗
[25]
P-C. Wu, J-W. Su, Y-L. Chung, L-Y. Hong, J-S. Ren, F-C. Chang, Y. Wu, H-Y. Chen, C-H. Lin, H-M. Hsiao, S-H. Li, S-S. Sheu, S-C. Chang, W-C. Lo, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh , K-T. Tang, C-I. Wu, M-F. Chang , A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices, 2022 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2022.
IEEE Xplore ↗
[26]
J-M. Hung, Y-H. Huang, S-P. Huang, F-C. Chang, T-H. Wen, C-I. Su, W-S. Khwa, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh , K-T. Tang, Y-D. Chih, T-Y. J. Chang, M-F. Chang , An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4 - 21.6TOPS/W for Edge-AI Devices, 2022 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2022.
IEEE Xplore ↗
[27]
Chih-Cheng Chen, Chih-Cheng Hsieh , A 12-ENOB Second-Order Noise Shaping SAR ADC with PVT-insensitive Voltage-Time-Voltage Converter, in 2021 IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2021.
IEEE Xplore ↗
[28]
Hsin-Yu Wu, Wei-Tse Kao, Harrison Hao-Yu Ku, Cheng-Te Wang, Chih-Cheng Hsieh , Ren-Shuo Liu, Kea-Tiong Tang, Chung-Chuan Lo , A Bio-Inspired Motion Detection Circuit Model for the Computation of Optical Flow: The Spatial-Temporal Filtering Reichardt Model, in 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS) , June. 2021.
IEEE Xplore ↗
[29]
Wen-Chieh Wu, Chen-Fu Yeh, Alexander James White, Cheng-Te Wang, Zuo-Wei Yeh, Chih-Cheng Hsieh , Ren-Shuo Liu, Kea-Tiong Tang, Chung-Chuan Lo , Integer Quadratic Integrate-and-Fire (IQIF): A Neuron Model for Digital Neuromorphic Systems, in 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS) , June. 2021.
IEEE Xplore ↗
[30]
Wei-Chih Lai, Tzu-Hsiang Hsu, Chih-Cheng Chen, Chih-Cheng Hsieh , A 12-Bit SAR ADC with Reference Voltage Ripple Suppression, in 2021 IEEE International Symp. on Circuits and Systems ( ISCAS ), May. 2021.
IEEE Xplore ↗
[31]
C-X. Xue, J-M. Hung, H-Y. Kao, Y-H. Huang, S-P. Huang, F-C. Chang, P. Chen, T-W. Liu, C-J. Jhang, C-I. Su, W-S. Khwa, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh , K-T. Tang, Y-D. Chih, T-Y. J. Chang, M-F. Chang , A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices, 2021 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2021.
IEEE Xplore ↗
[32]
J-W. Su, Y-C. Chou, R. Liu, T-W. Liu, P-J. Lu, P-C. Wu, Y-L. Chung, L-Y. Hung, J-S. Ren, T. Pan, S-H. Li, S-C. Chang, S-S. Sheu, W-C. Lo, C-I. Wu, X. Si, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh , K-T. Tang, M-F. Chang , A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b of Precision for AI Edge Chips, 2021 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2021.
IEEE Xplore ↗
[33]
You-Shin Chen, Tzu-Hsiang Hsu, Guan-Cheng Chen, Chien-Wen Chen, Chih-Cheng Hsieh , A Monolithic Optical Encoder Using CMOS Image Sensor with Background Light Cancellation, 2020 IEEE International Symp. on Circuits and Systems ( ISCAS ), Oct. 2020.
IEEE Xplore ↗
[34]
Tzu-Hsiang Hsu, Yen-Kai Chen, Jun-Shen Wu, Wen-Chien Ting, Cheng-Te Wang, Chen-Fu Yeh, Syuan-Hao Sie, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh , A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel, 2020 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2020.
IEEE Xplore ↗
[35]
J-W. Su, X. Si, Y-C. Chou, T-W. Chang, W-H. Huang, Y-N. Tu, R. Liu, P-J. Lu, T-W. Liu, J-H. Wang, Z. Zhang, H. Jiang, S. Huang, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh , K-T. Tang, S-S. Sheu, S-H. Li, H-Y. Lee, S-C. Chang, S. Yu, M-F. Chang , A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips, 2020 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2020.
IEEE Xplore ↗
[36]
C-X. Xue, T-Y. Huang, J-S. Liu, T-W. Chang, H-Y. Kao, J-H. Wang, T-W. Liu, S-Y. Wei, S-P. Huang, W-C. Wei, Y-R. Chen, T-H. Hsu, Y-K. Chen, Y-C. Lo, T-H. Wen, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh , K-T. Tang, M-F. Chang , A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices, 2020 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2020.
IEEE Xplore ↗
[37]
X. Si1, Y-N. Tu, W-H. Huang, J-W. Su, P-J. Lu, J-H. Wang, T-W. Liu, S-Y. Wu, R. Liu, Y-C. Chou, Z. Zhang, S-H. Sie, W-C. Wei, Y-C. Lo, T-H. Wen, T-H. Hsu, Y-K. Chen, W. Shih, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh , K-T. Tang, N-C. Lien, W-C. Shih, Y. He, Q. Li, M-F. Chang , A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips, 2020 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2020.
IEEE Xplore ↗
[38]
Chung-Yu Wu, Chih-Cheng Hsieh , Far-Wen Jih, Tai-Ping Sun and Sheng-Jenn Yang, A New Share-Buffered Direct-Injection Readout Structure for Infrared Detector, Infrared Technology XIX , Proc. SPIE, vol. 2020, pp. 57-64, 1993.
IEEE Xplore ↗
[39]
[Invited] Tzu-Hsiang Hsu, Yen-Cheng Chiu, Wei-Chen Wei, Yun-Chen Lo, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Meng-Fan Chang, and Chih-Cheng Hsieh , AI Edge Devices Using Computing-In-Memory and Processing-In-Sensor: From System to Device, 2019 IEEE International Electron Devices Meeting (IEDM) , Dec. 2019.
IEEE Xplore ↗
[40]
Tzu-Hsiang Hsu, R.-S. Liu, C.-C. Lo, K.-T. Tang, M.-F. Chang, and Chih-Cheng Hsieh , A 0.5V Real-time Computational CMOS Image Sensor with Programmable Kernel for Always-on Feature Extraction, 2019 IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2019.
IEEE Xplore ↗
[41]
Yi-Hsuan Lin and Chih-Cheng Hsieh , An Energy-Efficient 12b 20MS/s Time-Interleaved SAR ADC Using Shared Semi-Resting DAC Switching, 2019 IEEE International Conference on Analog VLSI circuits (AVIC) , Oct. 2019.
IEEE Xplore ↗
[42]
K.-T. Tang , W.-C. Wei, Z.-W. Yeh, T.-H. Hsu, Y.-C. Chiu, C.-X. Xue, Y.-C. Kuo, T.-H. Wen, M.-S. Ho, C.-C. Lo, R.-S. Liu, Chih-Cheng Hsieh and M.-F. Chang, Considerations of Integrating Computing-In-Memory and Processing-In-Sensor into Convolutional Neural Network Accelerators for Low-Power Edge Devices, 2019 IEEE Symposia on VLSI Circuits (VLSI Symposia) , Jun. 2019.
IEEE Xplore ↗
[43]
Yung-Te Chang, Min-Rui Wu, Chih-Cheng Hsieh , A 40MS/S 12-Bit Zero-Crossing Based SAR-Assisted Two-Stage Pipelined ADC with Adaptive Level Shifting, 2019 IEEE International Symp. on Circuits and Systems ( ISCAS ), May. 2019.
IEEE Xplore ↗
[44]
You-Shin Chen, Tzu-Hsiang Hsu, Chien-Wen Chen, and Chih-Cheng Hsieh , A Current-Mode Differential Sensing CMOS Imager for Optical Linear Encoder, 2019 IEEE International Symposium on VLSI Design, Automation and Test ( VLSI-DAT ), Apr. 2019.
IEEE Xplore ↗
[45]
C-X. Xue, W-H. Chen, J-S. Liu, J-F. Li, W-Y. Lin, W-E. Lin, J-H. Wang, W-C. Wei, T-W. Chang, T-C. Chang, T-Y. Huang, H-Y. Kao, S-Y. Wei, Y-C. Chiu, C-Y. Lee, C-C. Lo, Y-C. King, C-J. Lin, R-S. Liu, Chih-Cheng Hsieh , K-T. Tang, M-F. Chang , A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN-Based AI Edge Processors, 2019 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2019.
IEEE Xplore ↗
[46]
X. Si1, J-J. Chen1, Y-N. Tu1, W-H. Huang, J-H. Wang, W-C. Wei, S-Y. Wu, X. Sun, R. Liu, S. Yu, R-S. Liu1, Chih-Cheng Hsieh , K-T. Tang, Q. Li, M-F. Chang, Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN- Based Machine Learning, 2019 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2019.
IEEE Xplore ↗
[47]
Kwuang-Han Chang, and Chih-Cheng Hsieh , A Calibration-Free 0.7-V 13-bit 10-MS/s Full-Analog SAR ADC with Continuous-Time Feedforward Cascaded (CTFC) Op-Amps, 2018 IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2018.
IEEE Xplore ↗
[48]
Hsiang-Lin Chen, Sung-En Hsieh, Tzu-Hsiang Hsu, and Chih-Cheng Hsieh , A CMOS Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient Interference Rejections, 2018 IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2018.
IEEE Xplore ↗
[49]
H Chen , Y-C Chang, S-R Yeh, Chih-Cheng Hsieh , K-T Tang, P-H Hsieh, Y-T Liao, R Perumel, J-F Chuang, C-C Chang, Y-C Chen, S. H. Chen, S-E Hsieh, Y-P Chen, Y-T Chen, T-H Liu, Y-M Chang, W-C Lai, C-Y Wu, Y-H Chen, Y-C Weng, Development of a Multisite, Closed-loop Neuromodulator for the Theranosis of Neural Degenerative Diseases, 2018 IEEE Symposia on VLSI Circuits (VLSI Symposia) , Jun. 2018.
IEEE Xplore ↗
[50]
Sung-En Hsieh and Chih-Cheng Hsieh , A 0.4V 13b 270kS/s SAR-ISDM ADC with an Opamp-Less Time-Domain Integrator, 2018 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2018.
IEEE Xplore ↗
[51]
W-H. Chen, K-X. Li, W-Y. Lin, K-H. Hsu, P-Y. Li, C-H. Yang, C-X. Xue, E-Y. Yang, Y-K. Chen, Y-S. Chang, T-H. Hsu, Y-C. King, C-J. Lin, R-S. Liu, Chih-Cheng Hsieh , K-T. Tang, M-F. Chang , A 65nm 1Mb Nonvolatile Computing-in-Memory ReRAM Macro with Sub-16ns Multiply-and-Accumulate for Binary DNN AI Edge Processors, 2018 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2018.
IEEE Xplore ↗
[52]
Chen-Che Kao, Sung-En Hsieh, and Chih-Cheng Hsieh , A 0.5V 12-bit SAR ADC using Adaptive Time-Domain Comparator with Noise Optimization, 2017 IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2017.
IEEE Xplore ↗
[53]
Ting Liao, Nien-An Lee, and Chih-Cheng Hsieh , A CMOS Time of Flight (TOF) Depth Image Sensor with In-Pixel Background Cancellation and Sensitivity Improvement Using Phase Shifting Readout Technique, 2017 IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2017.
IEEE Xplore ↗
[54]
Tzu-Hsiang Hsu, and Chih-Cheng Hsieh , Wen-Hsu Chang, Hann-Huei Tsai and Chin-Fong Chiu, A CMOS Imaging Platform Using Single Photon Avalanche Diode Array in Standard Technology, 2017 IEEE Sensors Conference , Oct. 2017.
IEEE Xplore ↗
[55]
[Invited] Chih-Cheng Hsieh and Albert Yen-Chih Chiou, Low-voltage High-dynamic-range CMOS Imager with Energy Harvesting, 2016 International Workshop on Image Sensors and Imaging Systems (IWISS) , Nov. 2016.
IEEE Xplore ↗
[56]
Kuan-Lin Liu, Sheng-Yeh Lai, Chin-Fong Chiu, and Chih-Cheng Hsieh , A Time Delay Multiple Integration Linear CMOS Image Sensor for Multispectral Satellite Telemetry, 2016 IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2016.
IEEE Xplore ↗
[57]
Albert Yen-Chih Chiou, Sung-En Hsieh, Yan-Quan Pan, Chia-Chi Kuo, and Chih-Cheng Hsieh , An Integrated CMOS Optical Sensing Chip for Multiple Bio-Signal Detections, 2016 IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2016.
IEEE Xplore ↗
[58]
Kwuang-Han Chang, and Chih-Cheng Hsieh , A 12 bit 150 MS/s 1.5 mW SAR ADC with Adaptive Radix DAC in 40 nm CMOS, IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2016.
IEEE Xplore ↗
[59]
Sung-En Hsieh and Chih-Cheng Hsieh , A 0.44fJconversion-step 11b 600KSs SAR ADC with Semi-Resting DAC, 2016 IEEE Symposia on VLSI Circuits (VLSI Symposia) , Jun. 2016.
IEEE Xplore ↗
[60]
Sung-En Hsieh and Chih-Cheng Hsieh , A 0.3V 0.705fJ/Conversion-step 10-bit SAR ADC with Shifted Monotonic Switching Scheme in 90nm CMOS, 2016 IEEE International Symp. on Circuits and Systems ( ISCAS ), May. 2016.
IEEE Xplore ↗
[61]
Pei-Chen Lee, and Chih-Cheng Hsieh , A 0.4V 1.94fJ/Conversion-Step 10b 750kS/S SAR ADC with Input-Range-Adaptive Switching, 2016 IEEE International Symp. on Circuits and Systems ( ISCAS ), May. 2016.
IEEE Xplore ↗
[62]
Kwuang-Han Chang, and Chih-Cheng Hsieh , A 12b 10MS/s 18.9fJ/Conversion- step Sub-radix-2 SAR ADC, 2016 IEEE International Symposium on VLSI Design, Automation and Test ( VLSI-DAT ), Apr. 2016.
IEEE Xplore ↗
[63]
Chia-Chi Kuo, and Chih-Cheng Hsieh , A 132dB DR Readout IC with Pulse Width Modulation for IR Focal Plane Arrays, 2015 IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2015.
IEEE Xplore ↗
[64]
Albert Yen-Chih Chiou, and Chih-Cheng Hsieh , A 0.4V Self-Powered CMOS Imager with 140dB Dynamic Range and Energy Harvesting, 2015 IEEE Symposia on VLSI Circuits (VLSI Symposia), Jun. 2015.
IEEE Xplore ↗
[65]
Chih-Hao Lin, and Chih-Cheng Hsieh , A Dual-Mode CMOS Imager for Free-Space Optical Communication with Signal Light Source Tracking and Background Cancellation, 2015 International Image Sensor Workshop ( IISW ), Jun. 2015.
IEEE Xplore ↗
[66]
Sung-En Hsieh, Cheng-Kang Ho, and Chih-Cheng Hsieh , A 1.2V 1MS/S 7.65fJ/Conversion-Step 12-Bit Hybrid SAR ADC with Time-to-Digital Converter, 2015 IEEE International Symp. on Circuits and Systems ( ISCAS ), May. 2015.
IEEE Xplore ↗
[67]
Jin-Yi Lin, Kwuang-Han Chang, Chen-Che Kao, Shih-Chin Lo, Yan-Jiun Chen, Pei-Chen Lee, Chi-Hui Chen, Chin Yin, and Chih-Cheng Hsieh , An 8-bit Column-Shared SAR ADC for CMOS image Sensor Applications, 2015 IEEE International Symp. on Circuits and Systems ( ISCAS ), May. 2015.
IEEE Xplore ↗
[68]
Zheng-Wei Huang, Chin-Fong Chiu and Chih-Cheng Hsieh , An In-pixel Equalizer with kTC Noise Cancellation and FPN Reduction, 2015 IEEE International Symposium on VLSI Design, Automation and Test ( VLSI-DAT ), Apr. 2015.
IEEE Xplore ↗
[69]
[Invited] Chih-Cheng Hsieh , Chin Yin, Albert Yen-Chih Chiou and Chih-Lin Lee, Design of Low-voltage Low-Power CMOS Imager, 2014 Asian Image Sensors and Imaging Systems Symposium (AISISS) , Dec. 2014.
IEEE Xplore ↗
[70]
Yan-Jiun Chen, and Chih-Cheng Hsieh , A 0.4V 2.02fJ/Conversion-step 10-bit Hybrid SAR ADC with Time-domain Quantizer in 90nm CMOS, 2014 IEEE Symposia on VLSI Circuits (VLSI Symposia), Jun. 2014.
IEEE Xplore ↗
[71]
Shih-Wen Chiu, Jen-Ho Wanf, Kwuang-Han Chang, Hiang-Chiu Wu, Hsin Chen, Chih-Cheng Hsieh , Meng-Fan Chang, Guoxing Wang, Kea-Tiong Tang, A signal acquisition and processing chip with built-in cluster for chemiresistive gas sensor array, 2014 IEEE International New Circuits and Sysytems Conference (NEWCAS), Jun. 2014.
IEEE Xplore ↗
[72]
Chih-Hao Lin, Che-Chun Lin, Ren-Jr. Chen, and Chih-Cheng Hsieh , A Dual-Mode CMOS Image Sensor for Optical Wireless Communication, 2014 IEEE International Symposium on VLSI Design, Automation and Test ( VLSI-DAT ), Apr. 2014.
IEEE Xplore ↗
[73]
K-T. Tang, S-W. Chiu, C-H. Shih, C-L. Chang, C-M. Yang, D-J. Yao, J-H. Wang, C-M. Huang, H. Chen, K-H. Chang, Chih-Cheng. Hsieh , T-H. Chang, M-F. Chang, C-M. Wang, Y-W. Liu, T-J. Chen, C-H. Yang, H. Chiueh, J-M. Shyu, "A 0.5V 1.27mW Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia," 2014 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2014.
IEEE Xplore ↗
[74]
Chin Yin, and Chih-Cheng Hsieh , A 0.5V 34.4uW 14.28kfps 105dB Smart Image Sensor with Array-level Analog Signal Processing, 2013 IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2013
IEEE Xplore ↗
[75]
[Invited] Chih-Cheng Hsieh , Chin Yin, Albert Yen-Chih Chiou and Chih-Lin Lee, Low-voltage Low-power and Smart CMOS Image Sensor, 2013 Asian Symposium on Advanced Image Sensors and Imaging Systems in Hamamatsu, Oct. 2013.
IEEE Xplore ↗
[76]
Hsin-Han Chen, and Chih-Cheng Hsieh , An Inverter-based Capacitive Trans-impedance Amplifier Readout with Offset Cancellation and Temporal Noise Reduction for IR Focal Plane Array, 2013 International Symposium on Photoelectronic Detection and Imaging ( ISPDI ), June. 2013
IEEE Xplore ↗
[77]
Chin Yin, and Chih-Cheng Hsieh , A 1V 14kfps Smart CMOS Imager with Tracking and Edge-detection Modes for Biomedical Monitoring, 2013 IEEE International Symposium on VLSI Design, Automation and Test ( VLSI-DAT ), Apr. 2013
IEEE Xplore ↗
[78]
Chang-Yuan Liou, and Chih-Cheng Hsieh , A 2.4-to-5.2fJ/Conversion-step 10b 0.5-to-4MS/s SAR ADC with Charge Average Switching DAC in 90nm CMOS, 2013 IEEE International Solid-State Circuits Conference ( ISSCC ), Feb. 2013
IEEE Xplore ↗
[79]
[Invited] Chih-Cheng Hsieh and Meng-Ting Chung, An Ultra-Low Voltage CMOS Imager with Novel Pulse-Width-Modulation Readout, 2012 International Display Workshops (IDW), Dec. 2012
IEEE Xplore ↗
[80]
Chuan-Hung Hsiao, Wei-Lin Chen, and Chih-Cheng Hsieh , A 0.8 V 80.3 dB SNDR Stage-Shared GU Modulator with Chopper-Embedded Switched-Opamp for Biomedical Application, 2012 IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2012.
IEEE Xplore ↗
[81]
Jin-Yi Lin, Hsin-Yuan Huang, Chih-Cheng Hsieh , and Hung-I Chen A 0.05mm2 0.6V 500kS/s 14.3fJ/Conversion-step 11-bit Two-step Switching SAR ADC for 3-Dimensional Stacking CMOS Imager, 2012 IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2012.
IEEE Xplore ↗
[82]
Jui-Hsin Chang, Kuo-Wei Cheng, Chih-Cheng Hsieh , Wen-Hsu Chang, Hann-Huei Tsai and Chin-Fong Chiu, Linear CMOS Image Sensor with Time-Delay Integration and Interlaced Super-Resolution Pixel, 2012 IEEE Sensors Conference , Oct. 2012.
IEEE Xplore ↗
[83]
Wei-Fan Chou, Shang-Fu Yeh, and Chih-Cheng Hsieh , A 143dB 1.96% FPN Linear-Logarithmic CMOS Image Sensor with Threshold-Voltage Cancellation and Tunable Linear Range, 2012 IEEE Sensors Conference , Oct. 2012.
IEEE Xplore ↗
[84]
Shan-Ju Tsai, Yen-Chun Chen, Chih-Cheng Hsieh , Wen-Hsu Chang, Hann-Huei Tsai and Chin-Fong Chiu, A Column-Parallel SA ADC with Linearity Calibration for CMOS Imagers, 2012 IEEE Sensors Conference , Oct. 2012.
IEEE Xplore ↗
[85]
Hsin-Yuan Huang, Jin-Yi Lin, Chih-Cheng Hsieh , Wen-Hsu Chang, Hann-Huei Tsai and Chin-Fong Chiu, A 9.2b 47fJ/Conversion-Step Asynchronous SAR ADC with Input Range Prediction DAC Switching, 2012 IEEE International Symp. on Circuits and Systems ( ISCAS ), May. 2012.
IEEE Xplore ↗
[86]
Kuo-Wei Cheng, Chin Yin, Chih-Cheng Hsieh , Wen-Hsu Chang, Hann-Huei Tsai and Chin-Fong Chiu, Time-Delay Integration Readout with Adjacent Pixel Signal Transfer for CMOS Image Sensor, 2012 IEEE International Symposium on VLSI Design, Automation and Test ( VLSI-DAT ), Apr. 2012.
IEEE Xplore ↗
[87]
Meng-Ting Chung and Chih-Cheng Hsieh , A 0.5V 4.95µW 11.8fps PWM CMOS Imager With 82dB Dynamic Range and 0.055% Fixed-Pattern-Noise, 2012 IEEE International Solid-State Circuits Conference ( ISSCC ), Feb. 2012.
IEEE Xplore ↗
[88]
Kea-Tiong Tang; Shih-Wen Chiu; Meng-Fan Chang; Chih-Cheng Hsieh *; and Jyuo-Min Shyu, A wearable Electronic Nose SoC for healthier living, 2011 IEEE Biomedical Circuits and Systems Conference (BioCAS) , Nov. 2011.
IEEE Xplore ↗
[89]
Chin-Lin Lee and Chih-Cheng Hsieh , A 0.8V 64x64 CMOS Imager with Integrated Sense-and-Stimulus Pixel for Artificial Retina Applications, 2011 IEEE Asian Solid-State Circuits Conference ( ASSCC ), Nov. 2011.
IEEE Xplore ↗
[90]
Shang-Fu Yeh, Chih-Cheng Hsieh , Chiao-Jen Cheng and Chun-Kai Liu, A Novel Single Slope ADC Design for Wide Dynamic Range CMOS Image Sensors, 2011 IEEE Sensors Conference , Oct. 2011.
IEEE Xplore ↗
[91]
Lo-Wei Huang, Chih-Cheng Hsieh , Wen-Hsu Chang*, Ying-Zong Juang* and Chin-Fong Chiu*, A 1.8V Readout Integrated Circuit with Adaptive Transimpedance Control Amplifier for IR Focal Plane Arrays, 2011 IEEE Sensors Conference , Oct. 2011.
IEEE Xplore ↗
[92]
Chin Yin, Chih-Cheng Hsieh , Wen-Hsu Chang*, Ying-Zong Juang* and Chin-Fong Chiu*, An Information Sensor with In-Pixel-Processing for Geriatric Nursing, 2011 IEEE Sensors Conference , Oct. 2011.
IEEE Xplore ↗
[93]
Shang-Fu Yeh, Jin-Yi Lin, Chih-Cheng Hsieh , Ka-Yi Yeh* and Chung-Chi Jim Li*, A New CMOS Image Sensor Readout Structure for 3D Integrated Imagers, 2011 IEEE Custom Integrated Circuits Conference ( CICC ), Sep. 2011.
IEEE Xplore ↗
[94]
Chin-Lin Lee and Chih-Cheng Hsieh , A 0.6V CMOS Image Sensor with in-Pixel Biphasic Current Driver for Biomedical Application, 2011 IEEE International Symp. on Circuits and Systems ( ISCAS ), pp. 1455-1458, May. 2011.
IEEE Xplore ↗
[95]
Tsan-Jieh Chen , Chih-Hui Weng, Herming Chiueh*, Chih-Cheng Hsieh *, Shang-Fu Yeh, Wen-Hsu Chang, Ying-Zong Juang, Hann-Huei Tsai and Chin-Fong Chiu, The Prototype of Real-Time Image Pre-Processing System for Satellites' Remote Sensing, 2011 IEEE International Symp. on Circuits and Systems ( ISCAS ), pp. 1992-1996, May. 2011
IEEE Xplore ↗
[96]
Shang-Fu Yeh, Chih-Cheng Hsieh , Chin-Fong Chiu, and Hann-Huei Tsai, An Image Lag Free CMOS Image Sensor with Constant-Residue Reset, 2011 IEEE International Symposium on VLSI Design, Automation and Test ( VLSI-DAT ), Apr. 2011.
IEEE Xplore ↗
[97]
Sung-Min Chin and Chih-Cheng Hsieh , A New Rail-to-Rail Comparator with Adaptive Power Control for Low Power SAR ADCs in Biomedical Application, 2010 IEEE International Symp. on Circuits and Systems ( ISCAS ), pp. 1575-1578, May. 2010.
IEEE Xplore ↗
[98]
Chih-Cheng Hsieh , Wei-Yu Chen, and Chung-Yu Wu, A High Performance Linear Current Mode Image Sensor, 2009 IEEE International Symp. on Circuits and Systems ( ISCAS ), pp. 1273-1276, May. 2009.
IEEE Xplore ↗
[99]
Chih-Cheng Hsieh , Chung-Yu Wu, Far-Wen Jih, Tai-Ping Sun and Horng Chang, A New CMOS Readout Circuit Design for the IR FPA with Adaptive Gain Control and Current-Mode Background Suppression, 1996 IEEE International Symp. on Circuits and Systems , vol. 1, pp. 137-140, May. 1996.
IEEE Xplore ↗
[100]
Chih-Cheng Hsieh , Chung-Yu Wu, Far-Wen Jih, Tai-Ping Sun and Sheng-Jenn Yang, A New Switch-Current Integration Readout Structure for Infrared Focal Plane Array, Infrared Technology XX , Proc. SPIE, vol. 2269, pp. 718-726, Jul. 1994.
IEEE Xplore ↗

Domestic Conferences (45)

[1]
Po-Hsi Lee, Chih-Cheng Hsieh , A 435 KS/s 10-bit Column-Parallel Hybrid ADC Using Range-Partitioned Quantization with Asynchronous Charge-Injection and Single-Slope Conversion, 2025 VLSI Design/CAD Symposium , Kaohsiung, Taiwan, Aug 5-Aug 8, 2025.
[2]
Chun-Yi Wu, Chih-Cheng Hsieh , A 32×32 120.4dB Self-Calibrated Analog Counters with Extrapolation for SPAD Imager, 2025 VLSI Design/CAD Symposium , Kaohsiung, Taiwan, Aug 5-Aug 8, 2025.
[3]
Po- An Chen, Chih-Cheng Hsieh , A 312.5fps Vision Sensor with In-Pixel Timestamp Encoding for Low-Power EMD-Inspired Motion Estimation, 2025 VLSI Design/CAD Symposium , Kaohsiung, Taiwan, Aug 5-Aug 8, 2025.
[4]
Jia-Wei Ho, Chih-Cheng Hsieh , A Column-Parallel ROIC with Signal-Reconstructed Current-Mode Readout and Partial DC Cancellation for High-Linearity, Low-Noise Microbolometer Imaging, 2025 VLSI Design/CAD Symposium , Kaohsiung, Taiwan, Aug 5-Aug 8, 2025.
[5]
Yu-Tang Shen, Chih-Cheng Hsieh , A NMOS-Only Pulse-Width-Modulation CMOS Imager with Body Effect Mitigation Using Differential Comparison Technique, 2024 VLSI Design/CAD Symposium , Taichung, Taiwan, July 30-Aug 2, 2024.
[6]
Cheng-Jhe Li, Chih-Cheng Hsieh , A Digital Pixel Sensor with 0.43%/-0.1% Nonlinearity and 41μW Power Consumption Using Wide Swing PWM and Embedded 10-bit 3T-GC-eDRAM, 2024 VLSI Design/CAD Symposium , Taichung, Taiwan, July 30-Aug 2, 2024.
[7]
Hung-Po Kuo, Chih-Cheng Hsieh , A 12-BIT 150MS/S PIPELINED-SAR ADC WITH LOW DC GAIN AMPLIFIER, 2023 VLSI Design/CAD Symposium , Kaohsiung, Taiwan, Aug. 1-4, 2023.
[8]
Bao-Shu Liu, Chih-Cheng Hsieh , A Low-OSR 5th-Order Noise Shaping SAR ADC in a Two-Amplifier EF-EF-CIFF Structure with Low-Noise PVT-Robust V-T-V Converters, 2023 VLSI Design/CAD Symposium , Kaohsiung, Taiwan, Aug. 1-4, 2023.
[9]
Hsin Yu, Chih-Cheng Hsieh , A 53mK-NETD Low Power ROIC for 80*60 Microbolometer CMOS Thermal Image Sensor with Ultra High Dynamic Range, 2022 VLSI Design/CAD Symposium , Virtual Meeting, Taiwan, Aug. 2-5, 2022.
[10]
Min-Ruei Wu, Chih-Cheng Hsieh , A 400KS/s 62.6pJ/c.-s 10-bits Column-Parallel Hybrid ADC Using Self-Adaptive Charge-Injection Cell and Single-Slope Conversion, 2022 VLSI Design/CAD Symposium , Virtual Meeting, Taiwan, Aug. 2-5, 2022.
[11]
Chih-Cheng Chen, Chih-Cheng Hsieh , A 12-ENOB 2nd-order Noise Shaping SAR ADC with Voltage-Time-Voltage Converter, 2021 VLSI Design/CAD Symposium , Virtual Meeting, Taiwan, Aug. 4-7, 2021.
[12]
Yu-Tang Shen, Chi-Chun Chang, Yu-Hsiang Huang, Min-Yang Chiu, Guan-Cheng Chen, Chih-Cheng Hsieh , A 12-bit 350-kS/s Column-Parallel Single-Slope ADC Readout Circuit Using Charge-Pump Phase-Locked Loop and Double-Edge Triggered Gray Code Counter, 2020 VLSI Design/CAD Symposium , Taichung, Taiwan, Aug. 4-7, 2020.
[13]
Wei-Chih Lai, Chih-Cheng Chen, Chih-Cheng Hsieh , A 12-bit SAR ADC with Reference Voltage Ripple Suppression, 2020 VLSI Design/CAD Symposium , Taichung, Taiwan, Aug. 4-7, 2020.
[14]
[Best Paper Award] Tzu-Hsiang Hsu, Chih-Cheng Hsieh , A 0.5V Real-time Computational CMOS Image Sensor with Programmable Kernel for Always-on Feature Extraction, 2019 VLSI Design/CAD Symposium , Kaohsiung, Taiwan, Aug. 6-9, 2019.
[15]
You-Shin Chen, T.-H. Hsu, C.-W. Chen, Chih-Cheng Hsieh , A Low Noise Optical Encoder with Background Light Cancellation Using Photodiodes in Series, 2019 VLSI Design/CAD Symposium , Kaohsiung, Taiwan, Aug. 6-9, 2019.
[16]
Yi-Hsuan Lin, Chih-Cheng Hsieh , An Energy-Efficient 12b 20MS/s Time-Interleaved SAR ADC, 2019 VLSI Design/CAD Symposium , Kaohsiung, Taiwan, Aug. 6-9, 2019.
[17]
Min-Yang Chiu, Guan-Cheng Chen, Tzu-Hsiang Hsu, Chih-Cheng Hsieh , A 64x64 Pixels CMOS Image Sensor Using Pseudo Multiple Sampling with Column CDS, 2018 VLSI Design/CAD Symposium , Tainan, Taiwan, Aug. 7-10, 2018.
[18]
Hsiang-Lin Chen, Sung-En Hsieh, Tzu-Hsiang Hsu, Chih-Cheng Hsieh , A CMOS Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient Interferer Rejection, 2018 VLSI Design/CAD Symposium , Kenting, Taiwan, Aug. 7-10, 2018.
[19]
[Best Paper Award] Min-Rui Wu, Sung-En Hsieh, Chih-Cheng Hsieh , A 12-bit SAR ADC with split switching DAC, 2018 VLSI Design/CAD Symposium , Kenting, Taiwan, Aug. 7-10, 2018.
[20]
[Best Paper Award] Kwuang-Han Chang, Chih-Cheng Hsieh , A 5.3fJ/conv.-step 12b 50MS/s Full-Analog SAR ADC in 40nm CMOS, 2017 VLSI Design/CAD Symposium , Kenting, Taiwan, Aug. 2-5, 2017.
[21]
Albert Chiou, Chih-Cheng Hsieh , A 0.4V CMOS Imager with Adaptive-Multiple-Sampling Linear Response, HDR Imaging, and Energy Harvesting, 2017 VLSI Design/CAD Symposium , Kenting, Taiwan, Aug. 2-5, 2017.
[22]
Tzu-Hsiang Hsu, Chih-Cheng Hsieh , A Testing CMOS Image Sensor with High Sensitive Single Photon Avalanche Diode Array, 2017 VLSI Design/CAD Symposium , Kenting, Taiwan, Aug. 2-5, 2017.
[23]
[Paper Award] Kwuang-Han Chang, Chih-Cheng Hsieh , A 12b 150MS/s 1.5mW SAR ADC with Adaptive Radix in 40nm CMOS, 2016 VLSI Design/CAD Symposium , Kaohsiung, Taiwan, Aug. 2-5, 2016.
[24]
[Paper Award] Albert Chiou, Sung-En Hsieh, Yan-Quan Pan, Chia-Chi Kuo, Chih-Cheng Hsieh , An Integrated CMOS Optical Sensing Chip for Multi-Bio-Signal Detections, 2016 VLSI Design/CAD Symposium , Kaohsiung, Taiwan, Aug. 2-5, 2016.
[25]
[Best Paper] Chin Yin, Chin-Fong Chiu, Chih-Cheng Hsieh , A 32-stage 15-bit Digital Time-delay-integration Linear CMOS Image Sensor with Data Prediction Switching Technique, 2015 VLSI Design/CAD Symposium , Hualien, Taiwan, Aug. 4-7, 2015.
[26]
Pei-Chen Lee, Chih-Cheng Hsieh , A 0.4V 1.94fJ/conversion-step 10b 750kS/s SAR ADC with Input-Range-Adaptive Switching, 2015 VLSI Design/CAD Symposium , Hualien, Taiwan, Aug. 4-7, 2015.
[27]
Chia-Chi Kuo, Chih-Cheng Hsieh , A 1.8V 128dB DR Capacitive Trans-impedance Amplifier Readout Circuit for IR Focal Plane Arrays, 2015 VLSI Design/CAD Symposium , Hualien, Taiwan, Aug. 4-7, 2015.
[28]
Jui-Hsin Chang, Chin-Fong Chiu, Chih-Cheng Hsieh , A 12-stage Linear CMOS image sensor with APST-based Time Delay Integration, 2014 VLSI Design/CAD Symposium , Taichung, Taiwan, Aug. 5-8, 2014.
[29]
Zeng-Wei Huang, Chin-Fong Chiu, Chih-Cheng Hsieh , A Time- of- Flight CMOS Image Sensor with 54% Fixed Patten Noise Reduction, 2014 VLSI Design/CAD Symposium , Taichung, Taiwan, Aug. 5-8, 2014.
[30]
Sung-En Hsieh, Ho-Cheng Kang, Chih-Cheng Hsieh , A 12-bit SAR ADC with Voltage-to-Time Converter, 2014 VLSI Design/CAD Symposium , Taichung, Taiwan, Aug. 5-8, 2014.
[31]
Chin-Lin Lee, Chih-Cheng Hsieh , A Dual-Supply High Dynamic Range Sense-and-Stimulus Imager for Artificial Retina Applications, 2013 VLSI Design/CAD Symposium , Kaoshiung, Taiwan, Aug. 6-9, 2013.
[32]
Chin Yin, Chih-Cheng Hsieh , A 0.5V 34.4gW 105dB Smart Image Sensor with Array-level Analog Signal Processing, 2013 VLSI Design/CAD Symposium , Kaoshiung, Taiwan, Aug. 6-9, 2013.
[33]
Chen-Che Kao, E-Yuan Chang, and Chih-Cheng Hsieh , A Linear-Logarithmic CMOS Image Sensor with FPN Reduction for High Dynamic Range Applications, 2013 VLSI Design/CAD Symposium , Kaoshiung, Taiwan, Aug. 6-9, 2013.
[34]
Sheng-Hang Su, Wei-Lin Chen, Chih-Cheng Hsieh , Wen-Hsu Chang, Hann-Huei Tsai, and Chin-Fong Chiu, A 10-bit Column-Parallel SAR ADC with Calibration for Sensor Array Applications, 2013 Symposium on Engineering, Medicine, and Biology Applications (SEMBA) , Tainan, Taiwan, Feb. 1-3, 2013.
[35]
Po-Wei Chang, Chin Yin, Chih-Cheng Hsieh , Wen-Hsu Chang, Hann-Huei Tsai, and Chin-Fong Chiu, A Wide Dynamic Range CMOS Image Sensor with Dual Exposure Readout for Biomedical Imager, 2013 Symposium on Engineering, Medicine, and Biology Applications (SEMBA) , Tainan, Taiwan, Feb. 1-3, 2013.
[36]
Chuan-Hung Hsiao, Wei-Lin Chen, and Chih-Cheng Hsieh , A 0.7-V 81-dB DR Stage-Shared SC GU Modulator with Chopper-Embedded Switched-Opamp for Biomedical Application, 2012 VLSI Design/CAD Symposium , Kengting, Taiwan, Aug. 7-10, 2012.
[37]
Hsin-Yuan Huang, Pei-Chen Lee, Chi-Hui Chen, Yi-Ting Tseng, and Chih-Cheng Hsieh , A 17.4fJ/c-s 0.9V 10-bit 1MS/s Low-Power Asynchronous Successive Approximation Register Analog to Digital Converter, 2012 VLSI Design/CAD Symposium , Kengting, Taiwan, Aug. 7-10, 2012.
[38]
Wei-Fan Chou, Shang-Fu Yeh, and Chih-Cheng Hsieh , A Linear-Logarithmic CMOS Image Sensor with FPN Reduction and Tunable Response Curve, 2012 VLSI Design/CAD Symposium , Kengting, Taiwan, Aug. 7-10, 2012.
[39]
Kuo-Wei Cheng, Chin Yin, Chih-Cheng Hsieh , Wen-Hsu Chang, Hann-Huei Tsai and Chin-Fong Chiu, Design of Time -Delay Integration CMOS Readout with Adjacent Pixel Signal Transfer, 2012 Symposium on Engineering, Medicine, and Biology Applications (SEMBA) , Taichung, Taiwan, Feb. 11-13, 2012.
[40]
Chin Yin, Chih-Cheng Hsieh , Wen-Hsu Chang, Ying-Zong Juang and Chin-Fong Chiu, An Information Sensor with In-Pixel-Processing for Geriatric Nursing, 2011 VLSI Design/CAD Symposium , Yunlin, Taiwan, Aug. 2-5, 2011.
[41]
Hsin- Yuan Huang, Chih-Cheng Hsieh , Wen-Hsu Chang, Hann-Huei Tsai and Chin-Fong Chiu, A 10b Rail to Rail 500KS/s A SAR ADC with Reduced DAC Switching technique and Adaptive Settling Pulse for Biomedical Applications, 2011 VLSI Design/CAD Symposium , Yunlin, Taiwan, Aug. 2-5, 2011.
[42]
Shang-Fu Yeh, Jin-Yi Lin, Chih-Cheng Hsieh , Ka-Yi Yeh and Chung-Chi Jim Li, A New CMOS Image Sensor Design for 3D Integrated Imagers, 2011 VLSI Design/CAD Symposium , Yunlin, Taiwan, Aug. 2-5, 2011.
[43]
Chih-Lin Lee and Chih-Cheng Hsieh , A 0.8V 64x64 CMOS Imager with Integrated Sense-and-Stimulus Pixel for Artificial Retina Applications, 2011 Symposium on Engineering, Medicine, and Biology Applications (SEMBA) , Yunlin, Taiwan, Jul. 8-10, 2011.
[44]
Shang-Fu Yeh, Chih-Cheng Hsieh , Ka-Yi Yeh and Chung-Chi Jim Li, A Wide Dynamic Range CMOS Image Sensor for Bio-Applications, 2011 Symposium on Engineering, Medicine, and Biology Applications (SEMBA) , Yunlin, Taiwan, Jul. 8-10, 2011.
[45]
Chin-Lin Lee and Chih-Cheng Hsieh , A Pulse Frequency Modulation CMOS Image sensor for Biomedical Application, 2010 VLSI Design/CAD Symposium , Kaohsiung, Taiwan, Aug. 3-6, 2010.