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國立清華大學電機系 - 「積體電路設計探索實驗室」研究 介紹 Research Direction of 【IC-Dex Lab】 (IC-Design Exploration Lab) 黃錫瑜 Shi-Yu Huang, (syhuang@ee.nthu.edu.tw) Sept.3,2018 按此處可下載詳細介紹檔(PDF檔) (Detailed Description) |
主要方向 (General Direction): 本實驗室致力於『積體電路設計』、『積體電路設計自動化』、與『積體電路測試』等三方面技術之交互運用與融合之研究。
The research interests of this lab broadly cover VLSI design, automation, and testing, with prior experiences on formal verification, power estimation, fault diagnosis, and resilient nanometer SRAM Design. More recently, it is more concentrated on All-digital timing circuit designs, such as all-digital phase-locked loop (PLL), all-digital delay-locked loop (DLL), time-to-digital converter (TDC), and their applications to parametric fault testing for interconnects. From this lab, two research achievements including “eClock – a cell-based PLL compiler” and “PowerMixer – a multi-level power estimation software tool” were ever made commercial products.
目前專注的研究主題 ：
(1) Cell-Based Timing Circuits and Their Compilers Design
(PLL,DLL,TDC之設計,及其自動化編譯器設計)
(2) Delay Monitoring for Die-to-Die Interconnects in Multi-Die ICs
(多裸晶整合晶片之連接線速度監控)
(3) Scan Chain Diagnosis using Machine Learning Techniques
(使用機器學習之晶片掃描練診斷方法)
(4) DART (Data-Assisted Reliability and Testing for VLSI)
(資料驅動之晶片可靠度提升與測試方法)
過去研究主題：
(1) High-Yield SRAM Design for Nanometer Technology (高良率的奈米靜態記憶體電路設計)
(2) All-Digital PLL and Its Compiler (全數位鎖相迴路之自動化編譯器)
(3) SoC Multi-Core Power Estimation Tools (一系列可用於多核心系統晶片的功率消耗評估軟體)
(4) Quick & Cool Scan Test Methodology (快又低功耗的掃瞄鍊測試方法)
(5) Parametric Fault Testing for Die-to-Die Interconnects in 3D-IC
(三維晶片裸晶間連接線之參數型瑕疵測試)