Ta-Shun Chu
Associate Professor
Department of Electrical Engineering
National Tsing Hua University
Email : tschu@ee.nthu.edu.tw
Phone : +886-3-5742441
Address : Room 935, Delta Building, Dept. of Electrical Engineering,
National Tsing Hua University, Hsinchu 30013, Taiwan
Ta-Shun Chu (Member, IEEE) received the B.S. degree in civil engineering and the M.S. degree in applied mechanics from National Taiwan University, Taipei, Taiwan, in 2000 and 2002, respectively, and the Ph.D. degree in electrical engineering from the University of Southern California, Los Angeles, CA, USA, in 2010.,In 2010, he joined the Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan, where he is currently an Associate Professor and the Director of the NTHU EECS 820 Laboratory. His current research interests include millimeter wave, RF, analog, and mixed-mode integrated circuit development for radar systems.
Education
- Ph.D. in Electrical Engineering, University of Southern California, Los Angeles, CA, USA, Aug. 2004 – Sept. 2010
Dissertation: Silicon-Based Broadband Radar Architectures and Implementations.
Advisor: Dr. Hossein Hashemi
- Master of Science in Electrical Engineering, University of Southern California, Los Angeles, CA, USA, Jan. 2003 – Dec. 2004.
- Master of Science in Applied Mechanics, National Taiwan University, Taipei, Taiwan, Sept. 2000 – Jun. 2002.
Thesis: A New Addressable Corner Micro-Mirror Array for Optical Applications
Advisor: Dr. Long-Sun Huang
- Bachelor of Science in Civil Engineering, National Taiwan University, Taipei, Taiwan, Sept. 1996 – Jun. 2000.
Experience
- Associate Professor, Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan, Aug. 2015 – present.
- Assistant Professor, Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan, Sept. 2010 – Aug. 2015.
- Research Assistant, University of Southern California, Los Angeles, CA, USA, Sept. 2004 – Sept. 2010.
- Research Assistant, National Taiwan University, Taipei, Taiwan, Sept. 2000 – Jun. 2002.
Students Supervision
Dr. Ta-Shun Chu provides a favorable research environment and promising research directions for his students. He has supervised 7 Ph.D. and 53 M.S. students to successful completion and is currently supervising 2 Ph.D. students and 13 M.S. students at different stages of their research.
Current Students
| Name | Grade | Research Topic | Expected Grad. Year |
| Hu, Bo Syun | Ph.D. 6th Year | Fractional-N Digital PLL | 2021/07 |
| Wu, Yue Ming | Ph.D. 5th Year | Transmitter SoC for phased array | 2021/07 |
| Hsiao,Chih-Chuan | M.S. 2nd Year | Analog-to-Digital Converter | 2021/07 |
| Chang,Cheng-Hsun | M.S. 2nd Year | Analog-to-Digital Converter | 2021/07 |
| Su, Syuan-Fong | M.S. 2nd Year | Analog-to-Digital Converter | 2021/07 |
| Chen, Chih-Wen | M.S. 2nd Year | Analog-to-Digital Converter | 2021/07 |
| Lin,Yen-Yun | M. S. 1st Year | Clock and Data Recovery Circuit | 2022/07 |
| Chang,Chen-Ninh | M. S. 1st Year | Clock and Data Recovery Circuit | 2022/07 |
| Chang,Chi-Hua | M. S. 1st Year | Clock and Data Recovery Circuit | 2022/07 |
| Ho, I-Kai | M. S. 1st Year | Clock and Data Recovery Circuit | 2022/07 |
| Wu, Ting-Chun | M. S. 1st Year | Clock and Data Recovery Circuit | 2022/07 |
| Tsai, Pin-Hsin | M. S. 1st Year | Phase Locked Loop | 2022/07 |
| Peng, Te-Yu | M. S. 1st Year | Phase Locked Loop | 2022/07 |
| Wu,Ling-Chih | M. S. 1st Year | Phase Locked Loop | 2022/07 |
| Chen, Yu-Chun | M. S. 1st Year | Analog-to-Digital Converter | 2022/07 |
Graduated Students
| Name | Degree | Thesis Topic | Grad. Year | Present Work |
| Peng, Chun-Chieh |
Ph.D. | Designs of hybrid analog to digital converter | 2020 | MediaTek |
| Chou, Hao-Chung |
Ph.D. | A Single-RF-Port Mixer-First Duplexing Transceiver for Short-Range Radar Networks | 2019 | Tron Future Tech |
| Kao, Yu-Hsien |
Ph.D. | Broadband Radar System in CMOS Technology | 2017 | MediaTek |
| Tseng, Shao-Ting |
Ph.D. | Rotatable Cyclic Vernier Digital-to-Time Converter for Impulse Radar and Localization between Wireless Sensors | 2017 | MediaTek |
| Chen, Yen Ju |
Ph.D. | Applications and Implementations of Silicon-Based Oscillators at RF Region | 2016 | Novatek |
| Kai, Wen Tan |
Ph.D. | Design of Transmitter and Phase-locked Loop in CMOS for Microwave Ultra-wideband Automotive Radar Applications | 2015 | MediaTek |
| Lai, Chang-Ming |
Ph.D. | A direct sampling boradband radar system in CMOS technology | 2014 | MediaTek |
| Wang, Fu-Ching |
M. S. | A 640 MHz CMOS Continuous-Time Sigma-Delta Modulator with 10 MHz Bandwidth and 14-bit Resolution | 2020 | MediaTek |
| Lin, Szu-Yu |
M. S. | A Bandgap Circuit and a Delta-Sigma Modulator for Smart Temperature Sensor | 2020 | Novatek |
| Huang, Ya-Yun |
M. S. | A 35GHz Phase Locked Loop with Delta Sigma Modulator | 2020 | Novatek |
| Huang, Yu-Wen |
M. S. | A 10 Gbps Full-Rate Clock and Data Recovery Circuit Design for USB 3.1 Applications | 2020 | Novatek |
| Kao, Wei-Chih |
M. S. | A 12-Bit 80MS/s Successive-Approximation Analog-to-Digital Converter |
2020 | Texas Instrument |
| Chen, Chung-Kuang |
M. S. | A 10bit 1 GS/s DAC with a Low Complexity Foreground Calibration and Dynamic Element Matching | 2020 | PHISON |
| Tsai, Meng-Che |
M. S. | An Low-Dropout Linear Regulator With Bandgap Reference Voltage Source | 2020 | SuperFlower |
| Chu, Yu-Cheng |
M. S. | A 160MS/s 10-bit Successive-Approximation Analog-to-Digital Converter with Redundancy | 2020 | Amazing microelectronic |
| Lin, Hong-Wei |
M. S. | A CMOS 2-Gbps LVDS transmitter with 8:1 serialization for ADC processing | 2019 | Leadtrend |
| Tseng, Tung-En |
M. S. | A Second-Order Delta-Sigma Modulator for CMOS Smart Temperature Sensor | 2019 | Taiwan Power Company |
| Sung, Yao-Hsien |
M. S. | An Application of Baseband Analog Circuit Design in the Back-End System of CMOS Radar | 2019 | MediaTek |
| Peng, Chien-Wei |
M. S. | A 10-Bit 4-GS/s Current-Steering DAC with Dynamic Element Matching Techniques | 2019 | Novatek |
| Yang, Zong-Han |
M. S. | A 8~12Gb/s Full-Rate CDR with Continuous-Time Linear Equalization and Deserializer | 2018 | Focaltech |
| Chang, Yu-Hao |
M. S. | A 35GHz Phase Locked Loop with Delta Sigma Modulator | 2018 | Focaltech |
| Gao, Jia-Hong |
M. S. | A 4.825GHz Fractional-N All Digital Phase Lock Loop w/i Gated Ring Oscillator based TDC | 2018 | TSMC |
| Fan, Yi-Lin |
M. S. | A 6.2 ~ 7 GHz Spread-Spectrum Phase-Locked Loop w/i Delta-Sigma Modulator | 2018 | TSMC |
| Wei, Hsu-Chih |
M. S. | 4.825GHz Fractional-N TDC-Based All-Digital Phase-Locked Loop w/i Sigma-Delta Modulator Noise Cancellation | 2018 | Novatek |
| Chang, Ching-Ho |
M. S. | A 50MS/s SNDR 60dB 7Bit Successive-Approximation ADC w/i Noise Shaping | 2018 | Quanta Computer lnc. |
| Ma, Yu-Qian |
M. S. | A 10-Bit 1-GS/s Current-Steering DAC with Improved Dynamic-Performance Techniques | 2018 | Novatek |
| Lin, Pin-Hong |
M. S. | A 160MS/s 10-bit Successive-Approximation Analog-to-Digital Converter | 2018 | RealTek |
| Lin, Yi-Jui |
M. S. | A Delta-Sigma Phase Locked Loop working at 9 ~ 11 GHz | 2017 | GUC |
| Chen, Wei-Tsuen |
M. S. | A Delta-Sigma Phase Locked Loop with 2.8‐4.8 GHz tuning range | 2017 | MediaTek |
| Wei, Li-Fan |
M. S. | A 10-Bit 1-GS/s Current-Steering DAC with Foreground Calibration Method | 2017 | MediaTek |
| Wu, Po Chun |
M. S. | Time-interleaved Successive-Approximation Analog-to-Digital Converter with Redundancy | 2016 | ILITek |
| Jiang, Ru Hui |
M. S. | Low Dropout Regulator for Successive Approximation Analog to Digital Converter | 2016 | Micron |
| Liao, Chao Han |
M. S. | A 150MS/s 10bits Hybrid SAR ADC with Time-domain analysis | 2016 | Macronix |
| Wang, Bang Zhong |
M. S. | An Analog Baseband Circuit Design for the Back-End Circuit of Receiver in CMOS Radar System | 2016 | Fitipower |
| Wei, Ting Lun |
M. S. | A 8GHz Phase Locked Loop With Phase Rotated Function | 2015 | Novatek |
| Chen, Li Wei |
M. S. | A 6.5GHz Phase-Locked Loop with Linear phase shifter | 2015 | Anpec |
| Chen, Yan Hao |
M. S. | 1.09375GHz Delta Sigma Phase Lock Loop | 2015 | TSMC |
| Hu, Bo Syun |
M. S. | Digital-to-Time Converter for Impulse Radar with Time Resolution of 10ns/5700 and 10ns | 2015 | NTHU Ph.D Candidate |
| Liou, Meng Rong |
M. S. | An Analog Baseband Circuit Design for Director Sampling CMOS Radar System | 2015 | ILITek |
| Lin, Jing Heng |
M. S. | A 100MS/s Successive-Approximation Analog-to-Digital Converter with Redundancy | 2015 | ILITek |
| Wu, Yi Siang |
M. S. | Time Analysis SAR ADC and 1GS/s 6Bits Pipelined ADC | 2015 | TSMC |
| Wang, Yi Hung |
M. S. | Multi-channel Time-interleaved Analog-to-Digital Converter | 2015 | TSMC |
| Lin Si-Cheng |
M. S. | A Second-Order Delta-Sigma Modulator for Biomedical Signal Application | 2014 | RealTek |
| Hsieh, I-Hao |
M. S. | A Discrete Time Second Order Feed-Forward Delta Sigma Analog-to- Digital Converter | 2014 | Novatek |
| Chiu, Yun-Hui |
M. S. | Phase Locked Loop with Frequency-shift Magnetic Biosensor | 2014 | Novatek |
| Lee, Po-Chen |
M. S. | A Wideband Class-AB Power Amplifier in 65nm CMOS | 2014 | GUC |
| Huang, Chien-Hsing |
M. S. | Serial to Parallel Interface (SPI slave) | 2014 | Faraday |
| Jheng, Li-Wei |
M. S. | A Timing Circuitry of UWB Impulse Radar Achieving 1.5ps Time Resolution over 100ns | 2014 | Arts and Cultural Services –Singer |
| You, Cheng-Han |
M. S. | Design of MASH 1-1 Delta-Sigma Modulator for Frequency Synthesizer Applications | 2013 | Faraday |
| Lu, Huan Ting |
M. S. | A 35 GHz Phase Locked Loop With Phase Rotated Function | 2013 | Sunplus |
| Yang, Chih-Yuan |
M. S. | Serial data to Parallel data Interface | 2013 | Faraday |
| Wu Cheng-Yuan |
M. S. | Time-domain Model Analysis of Transmission Line in Very Large Scale Integrated Circuits and Systems | 2013 | KYEC |
| Hsu, Chih‐Chieh |
M. S. | Some issues: drug advisory electronic records, divider and transmission line | 2013 | LITEON |
| Zeng, Jyun-Syuan |
M. S. | A Successive-Approximation Analog-to-Digital Converter with half capacitance | 2013 | Focaltech |
| Lai, Shr-Chau |
M. S. | S-band and V-band Class AB Power Amplifiers | 2012 | RealTek |
| Huang, June-Wei |
M. S. | A 60 GHz Wide Tuning Range Phase Locked Loop | 2012 | Sunplus |
| Chung, Feng-Hsu |
M. S. | A 1-10 GHz Wide Tuning Range Phase Locked Loop | 2012 | ITRI |
| Kao, ChenKai |
M. S. | A Direct Sampling Receiver Frontend Circuit Design | 2012 | ILITek |
| Yen, Chia-Fung |
M. S. | A SAR ADC Design for Director Sampling CMOS Radar System | 2012 | Novatech |
| Yu, Liu-Yuan |
M. S. | A SAR ADC Design for Monolithic CMOS Radar System | 2011 | TSMC |