Ren-Shuo Liu is the first author or corresponding author of several top-tier papers, including ASPLOS, USENIX ATC, USENIX FAST, ESSCIRC, DAC, and ICCAD. Ren-Shuo Liu also co-authors several other top-tier papers including ISSCC, VLSI Symposia, and ASSCC.

International Conference Papers

  1. Tzu-Hsiang Hsu, Yen-Kai Chen, Jun-Shen Wu, Wen-Chien Ting, Cheng-Te Wang, Chen-Fu Yeh, Syuan-Hao Sie, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, and Chih-Cheng Hsieh*, “A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel,” International Solid-State Circuits Conference (ISSCC ’20), San Francisco, USA, Feb. 16-20, 2020.
  2. Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Zhixiao Zhang, Hongwu Jiang, Shanshi Huang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shyh-Shyuan Sheu, Sih-Han Li, Heng-Yuan Lee, Shih-Chieh Chang, Shimeng Yu, and Meng-Fan Chang*, “A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips,” International Solid-State Circuits Conference (ISSCC ’20), San Francisco, USA, Feb. 16-20, 2020.
  3. Cheng-Xin Xue, Tsung-Yuan Huang, Je-Syu Liu, Ting-Wei Chang, Hui-Yao Kao, Jing-Hong Wang, Ta-Wei Liu, Shih-Ying Wei, Sheng-Po Huang, Wei-Chen Wei, Yi-Ren Chen, Tzu-Hsiang Hsu, Yen-Kai Chen, Yun-Chen Lo, Tai-Hsing Wen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, and Meng-Fan Chang*, “A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices,” International Solid-State Circuits Conference (ISSCC ’20), San Francisco, USA, Feb. 16-20, 2020.
  4. Xin Si, Yung-Ning Tu, Wei-Hsing Huanq, Jian-Wei Su, Pei-Jung Lu, Jing-Hong Wang, Ta-Wei Liu, Ssu-Yen Wu, Ruhui Liu, Yen-Chi Chou, Zhixiao Zhang, Syuan-Hao Sie, Wei-Chen Wei, Yun-Chen Lo, Tai-Hsing Wen, Tzu-Hsiang Hsu, Yen-Kai Chen, William Shih, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Nan-Chun Lien, Wei-Chiang Shih, Yajuan He, Qiang Li, and Meng-Fan Chang*, “A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips,” International Solid-State Circuits Conference (ISSCC ’20), San Francisco, USA, Feb. 16-20, 2020.
  5. Yun-Chen Lo, Yu-Chun Kuo, Yun-Sheng Chang, Jian-Hao Huang, Jun-Shen Wu, Wen-Chien Ting, Tai-Hsing Wen, and Ren-Shuo Liu*, Physically-Tightly-coupled, Logically-Loosely-coupled, Near-Memory BNN Accelerator (PTLL-BNN),” European Solid-State Circuits Conference (ESSCIRC ’19), Krakow, Poland, Sep. 23-26, 2019.
  6. Tzu-Hsiang Hsu, Yen-Kai Chen, Tai-Hsing Wen, Wei-Chen Wei, Yi-Ren Chen, Fu-Chun Chang, Hyunjoon Kim, Qian Chen, Bongjin Kim, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, and Chih-Cheng Hsieh*, “A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction,” Asian Solid-State Circuits Conference (ASSCC ’19), Macao, China, Nov. 4-6, 2019. (Best Design Award)
  7. Tzu-Hsiang Hsu, Yen-Cheng Chiu, Wei-Chen Wei, Yun-Chen Lo, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Meng-Fan Chang, and Chih-Cheng Hsieh*, “AI Edge Devices Using Computing-In-Memory and Processing-In-Sensor: From System to Device,” International Electron Devices Meeting (IEDM ’19), San Francisco, USA, Dec. 7-11, 2019.
  8. Yun-Sheng Chang and Ren-Shuo Liu*, “OPTR: Order-Preserving Translation and Recovery Design for SSDs with a Standard Block Device Interface,” USENIX Annual Technical Conference (ATC '19), Renton, USA, Jul. 10-12, 2019. (acceptance rate: 71/356=19.9%)
  9. Kea-Tiong Tang, Wei-Chen Wei, Zuo-Wei Yeh, Tzu-Hsiang Hsu, Yen-Cheng Chiu, Cheng-Xin Xue, Yu-Chun Kuo, Tai-Hsing We, Mon-Shu Ho, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, and Meng-Fan Chang, “Considerations of Integrating Computing-In-Memory and Processing-In-Sensor into Convolutional Neural Network Accelerators for Low-Power Edge Devices,” Symposia on VLSI Technology & Circuits (VLSI '19), Kyoto, Japan, Jun. 9-14, 2019.
  10. Yu-Chun Kuo, Ruei-Fong Chiu, and Ren-Shuo Liu*, “Long-Term JPEG Data Protection and Recovery for NAND Flash-Based Solid-State Storage,” International Conference on Massive Storage Systems and Technology (MSST '19), Santa Clara, USA, May 20-24, 2019. (acceptance rate: 27/71=38%)
  11. Cheng-Hsuan Cheng and Ren-Shuo Liu*, “AIP: Saving the DRAM Access Energy of CNNs Using Approximate Inner Products,” International Conference on Artificial Intelligence Circuits and Systems (AICAS '19), Hinchu, Taiwan, Mar. 18-20, 2019.
  12. Cheng-Xin Xue, Wei-Hao Chen, Je-Syu Liu, Jia-Fang Li, Wei-Yu Lin, Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Ting-Wei Chang, Tung-Cheng Chang, Tsung-Yuan Huang, Hui-Yao Kao, Shih-Ying Wei, Yen-Cheng Chiu, Chun-Ying Lee, Chung-Chuan Lo, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, and Meng-Fan Chang*, “A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors,” International Solid-State Circuits Conference (ISSCC '19), San Francisco, USA, Feb. 17-21, 2019.
  13. Xin Si, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, and Meng-Fan Chang*, “A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning,” International Solid-State Circuits Conference (ISSCC '19), San Francisco, USA, Feb. 17-21, 2019.
  14. Ren-Shuo Liu*, Yun-Chen Lo, Yuan-Chun Luo, Chih-Yu Shen, and Cheng-Ju Lee, “DrowsyNet: Convolutional Neural Networks with Runtime Power-Accuracy Tunability using Inference-Stage Dropout,” International Symposium on VLSI Design, Automation and Test (VLSI-DAT '18), Hsinchu, Taiwan, April 16-19, 2018.
  15. Wei-Hao Chen, Kai-Xiang Li, Wei-Yu Lin, Kuo-Hsiang Hsu, Pin-Yi Li, Cheng-Han Yang, Cheng-Xin Xue, En-Yu Yang, Yen-Kai Chen, Yun-Sheng Chang, Tzu-Hsiang Hsu, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, and Meng-Fan Chang*, “A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors,” International Solid-State Circuits Conference (ISSCC '18), San Francisco, USA, Feb. 11-15, 2018.
  16. Ren-Shuo Liu* and Jian-Hao Huang, “DI-SSD: Desymmetrized Interconnection Architecture and Dynamic Timing Calibration for Solid-State Drives,” Asia and South Pacific Design Automation Conference (ASP-DAC '18), Jeju, Korea, Jan. 22-25, 2018. (acceptance rate: 88/271=32%)
  17. Ren-Shuo Liu*, Yun-Sheng Chang, and Chih-Wen Hung, “VST: A Virtual Stress Testing Framework for Discovering Bugs in SSD Flash-Translation Layers,” International Conference on Computer-Aided Design (ICCAD '17), Irvine, USA, Nov. 13-17, 2017. (acceptance rate:105/339=31%)
  18. R.-S. Liu, M.-Y. Chuang, C.-L. Yang, C.-H. Li, K.-C. Ho, and H.-P. Li, “EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs,” Design Automation Conference (DAC '14), San Francisco, USA, June 1-5, 2014
  19. “NVM Duet: Unified Working Memory and Persistent Store Architecture,” R.-S. Liu, D.-Y. Shen, C.-L.Yang, S.-C. Yu, and C.-Y. M. Wang, International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '14), Salt Lake City, USA, March 1-5, 2014
  20. R.-S. Liu, C.-L. Yang, C.-H. Li, and G.-Y. Chen, “DuraCache: A Durable SSD Cache Using MLC NAND Flash,” Design Automation Conference (DAC '13), Austin, USA, June 2-6, 2013
  21. R.-S. Liu, C.-L. Yang, and W. Wu, “Optimizing NAND Flash-Based SSDs via Retention Relaxation,” USENIX Conference on File and Storage Technologies (USENIX FAST '12), San Jose, USA, February 14-17, 2012
  22. R.-S. Liu, Y.-C. Tsai, and C.-L. Yang, “Parallelization and characterization of GARCH option pricing on GPUs,” IEEE International Symposium on Workload Characterization (IISWC '10), Atlanta, USA, December 2-4, 2010

International Journal Papers

  1. Cheng-Xin Xue, Wei-Hao Chen, Je-Syu Liu, Jia-Fang Li, Wei-Yu Lin, Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Tsung-Yuan Huang, Ting-Wei Chang, Tung-Cheng Chang, Hui-Yao Kao, Yen-Cheng Chiu, Chun-Ying Lee, Ya-Chin King, Chrong-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, and Meng-Fan Chang*, “Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors,” IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 1, pp. 203-215, Jan. 2020.
  2. Xin Si, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, and Meng-Fan Chang*, “A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors,” IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 1, pp. 189-202, Jan. 2020.
  3. Wei-Hao Chen, Chunmeng Dou, Kai-Xiang Li, Wei-Yu Lin, Pin-Yi Li, Jian-Hao Huang, Jing-Hong Wang, Wei-Chen Wei, Cheng-Xin Xue, Yen-Cheng Chiu, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, J. Joshua Yang, Mon-Shu Ho, and Meng-Fan Chang*, “CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors,” Nature Electronics 2, pp. 420–428, 2019.