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Publications

Conferences

  1. Hau Hsu, J.-J. Liou, Z.-H. Gao, and T.-S. Hsu, Post-silicon test flow for aging prediction, IEEE 26th Asian Test Symposium (ATS) 2017
  2. T.-S. Hsu, C.-C. Wu, C.-W. Hsu, C.-T. Huang, J.-J. Liou, Y.-H. Chen, J.-M. Lu, Design space exploration with a cycle-accurate systemC/TLM DRAM controller model, International Symposium on VLSI Design, Automation and Test (VLSI-DAT) 2017
  3. Y.-J. Shih, C.-T. Huang, J.-J. Liou, J.-Y. Lai, C.-W. Wang, C.-F. Wu, Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model, International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2017
  4. J.-J. Liou, M.-T. Hsieh, J.-F. Cherng, H. H. Chen, Cost reduction of system-level tests with stressed structural tests and SVM, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) 2015
  5. H.-W. Chien, J.-Y. Lai, C.-C. Wu; C.-T. Huang, T.-S. Hsu. J.-J. Liou, Design of a scalable many-core processor for embedded applications, Asia and South Pacific Design Automation Conference (ASP-DAC), 2015
  6. T.-S. Hsu, J.-L. Chiu, C.-K. Yu, J.-J. Liou, A fast and accurate network-on-chip timing simulator with a flit propagation model, Asia and South Pacific Design Automation Conference (ASP-DAC), 2015
  7. J.-Y. Chiang, J.-H. Kuo, T.-S. Hsu, J.-J. Liou, “Chip Clustering with Mutual Information on Multiple Clock Tests and its Application to Yield Tuning”, International Conference on Computer Design (ICCD) 2014
  8. J.-Y. Lai, C.-T. Huang, T.-S. Hsu, J.-J. Liou, T.-H. Yeh, L.-C. Cheng, J.-M. Lu, "Methodology of Exploring ESL/RTL Many-Core Platforms for Developing Embedded Parallel Applications", IEEE SOC Conference, 2014
  9. S.-Y. Hsu, T.-S. Hsu and J.-J. Liou, “A Region-Based Framework for Design Feature Identification of Systematic Process Variations,” in Asian Test Symposium (ATS) 2013
  10. J.-Y. Lai, P.-Y. Chen, Y.-H. Chen, T.-S. Hsu, C.-T. Huang and J.-J. Liou, "Design of High-Throughput Inter-PE Communication with Application-Level Flow Control Protocol for Many-Core Architecture", ACM Workshop on Many-core embedded systems (MES) 2013.
  11. J.-Y. Lai, P.-Y. Chen, T.-S. Hsu, C.-T. Huang and J.-J. Liou, "Design and analysis of a many-core processor architecture for multimedia applications", Asia-Pacific Signal and Information Processing Association (APSIPA) Annual Submit & Conference, 2012.
  12. J.-H. Kuo, T. -S. Hsu, J. -J. Liou, "Test Cost Reduction for Performance Yield Recovery by Classification of Multiple-Clock Test Data", Asian Test Symposium (ATS) 2012
  13. Ming Gao, P. Lisherness, K. T. Cheng, J.-J. Liou, On Error Modeling of Electrical Bugs for Post-Silicon Timing Validation, Asia and South Pacific Design Automation Conference (ASP-DAC), 2012
  14. Chin-Fu Li, et al. "A Low-Cost Wireless Interface with No External Antenna and Crystal Oscillator for Cm-Range Contactless Testing", DAC 2011.
  15. Jing-Jia Liou, et al. "Diagnosis-assisted Supply Voltage Configuration to Increase Performance Yield of Cell-Based Designs", ASPDAC 2011.
  16. IEEE Workshop on RTL and High Level Testing, “A Study of Software-Level Delay Fault Simulation for JPEG Decoder Application on CMP”, Shun-Yen Lu, Tso-Hua Chien and Jing-Jia Liou, Nov. 2009.
  17. IEEE Asian Test Symposium, “A Non-intrusive and Accurate Inspection Method for Segment Delay Variabilities”, Ying-Yen CHEN, Jing-Jia LIOU, ATS 2009.
  18. IEEE Asian Test Symposium, “Multiple-Core under Test Architecture for HOY Wireless Testing Platform”, Sung-Yu CHEN, Ying-Yen CHEN, Jing-Jia LIOU, ATS 2009.
  19. International Conference on IC Design & Technology, “Timing Yield Estimation with Clock Network Correlations by Propagating Discrete Probability Distributions”, L. Yu, C. Shih, J. Liou and Y. Shin, May, 2009.
  20. IEEE Asian Test Symposium, “High Quality Pattern Generation for Delay Defects with Functional Sensitized Paths,” Ming-Ting HSIEH, Shun-Yen LU, Jing-Jia LIOU, Augusli KIFLI, ATS 2008.
  21. IEEE Asian Test Symposium, “Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques,” Chun-Kai HSU, Li-Ming DENQ, Mao-Yin WANG, Jing-Jia LIOU, Chih-Tsun HUANG, Cheng-Wen WU, ATS 2008.
  22. IEEE International Test Synthesis Workshop, “Wireless Testing of RAM Chips by HOY: Methodology, Architecture, and Prototype Implementation”, T.-Y. Chang, C.-T. Huang, J.-J. Liou, C.-W. Wu, H.-P. Ma, C.-C. Tien, C.-H. Wang, C.-U. Yang, ITSW 2008.
  23. IEEE International Test Synthesis Workshop, “Improving the Efficiency of Scan Test on Wireless HOY Test Platform,” C.-W. Tzeng, C.-Y. Lin, S.-Y. Huang, C.-T. Huang, J.-J. Liou, H.-P. Ma, C.-W. Wu, ITSW 2008., NSC96-2220-E-007-002
  24. IEEE International Test Synthesis Workshop, “Automatic Wrapper Synthesis and Test Program Generation for Packet-based ATE Platforms,” Y.-Y. Chen, C.-U. Yang, S.-Y. Chen, J.-J. Liou, ITSW 2008., NSC96-2220-E-007-002
  25. IEEE International Test Conference, Nov 2007, “An Efficient SAT-based Path Delay Fault ATPG With an Unified Sensitization Model,” Shun-Yen Lu, Ming-Ting Hsieh, and Jing-Jia Liou, ITC 2007, NSC96-2220-E-007-002
  26. IEEE SOC Conference, Sep 2007, “A Prototype of a Wireless-based Test System,” , Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu, Ching-Cheng Tien, Chih-Hu Wang, Hsi-Pin Ma, Ying-Yen Chen, Yueh-Chih Hsu, Li-Ming Deng, Chien-Jung Chiu, Young-Wey Li and Chieh-Ming Chang, SOCC 2007, NSC96-2220-E-007-002
  27. IEEE Design Automation Conference, June 2007, “Extraction of Statistical Timing Profiles Using Test Data, “ Y.-Y. Chen, J.-J. Liou , DAC 2007., NSC96-2220-E-007-026
  28. IEEE VLSI Test Symposium, “Handling Pattern-Dependent Delay Faults in Diagnosis, “ J.-W. Chen, Y.-Y. Chen, J.-J. Liou , VTS, May 2007. NSC95-2220-E-007-013
  29. IEEE International Conference on Computer Aided Design, Nov 2006, San Jose USA, Exploring Linear Structures of Critical Path Delay Faults to Reduce Test Efforts, Shun-Yen Lu, Pei-Ying Hsieh and Jing-Jia Liou, ICCAD 2006, NSC95-2220-E-007-013
  30. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, October 2006, “Enhancing Diagnosis Resolution For Delay Faults by Path Extension Method,“, Ying-Yen Cheng, and Jing-Jia Liou, DFT 2006. NSC95-2220-E-007-038
  31. IEEE International Test Conference, Nov 2005, Austin, Tx. USA, Diagnosis Framework for Locating Failed Segments of Path Delay Faults, Ying-Yen Chen, Ming-Ping Kuo and Jing-Jia Liou, ITC 2005, NSC94-2220-E-007-034
  32. IEEE VLSI Test Symposium, "A BIST Scheme for FPGA Interconnect Delay Faults," Chun-Chieh Wang, " Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang and Cheng-Wen Wu, VLSI Test Symposium VTS 2005. NSC94-2220-E-007-002
  33. IEEE VLSI-TSA International Symposium on VLSI Design, Automation, and Test, April 2005,"Delay Defect Coverage for FPGA Test Configurations Based on Statistical Evaluation", Hsiang-Chieh Liao, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang and Cheng-Wen Wu, VLSI-TSA-DAT, 2005., NSC94-2220-E-007-002
  34. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, October 2004, “An application-independent delay testing methodology for island-style FPGA “, Yen-Lin Peng, Jing-Jiao Liu, Chich-Tsun Huang, Cheng-Wen Wu, Proceedings, DFT 2004, NSC94-2220-E-007-002
  35. IEEE Design Automation Conference, June 2003, Krstic, A.; Wang, L.-C.; Cheng, K.-T.; Liou, J.-J.; Mak, T.M., “Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models,” Proceedings - DAC, 2003, p 668-673, NSC92-2220-E-007-005
  36. IEEE DATE 2003, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, "Delay Defect Diagnosis Based Upon Statistical Timing Models -- The First Step," in Proc. DATE 2003, NSC92-2220-E-007-005.
  37. IEEE VLSI Test Symposium, April 2003, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, “Diagnosis of Delay Defects Using Statistical Timing Models," in Proc. IEEE VLSI Test Symposium, April 2003. (EI), NSC92-2220-E-007-005
  38. IEEE ISQED, Angela Krstic, Jing-Jia Liou, Kwang-Ting Cheng, Li-C. Wang,"On Structural Vs. Functional Testing for Delay Faults," in Proc. ISQED, 2003., NSC92-2220-E-007-005
  39. ACM/IEEE ASP Design Automation Conference, Jan., 2003, Jing-Jia Liou, Li-C. Wang, Angela Krstic, Kwang-Ting Cheng, "Experience in Critical Path Selection For Deep Sub-Micron Delay Test and Timing Validation," Proc. ACM/IEEE ASP-DAC Jan., 2003
  40. IEEE International Conference on Computer Aided Design, Nov 2002, San Jose USA, On Theoretical and Practical Considerations of Path Selection For Delay Fault Testing, Jing-Jia Liou, Li-C. Wang and Kwang-Ting Cheng, International Conference on Computer Aided Design (ICCAD) 2002.
  41. IEEE International Test Conference, Oct 2002, Atlanta USA, Analysis of Delay Test Effectiveness with Multiple-Clock Schemes, Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur and Thomas W. Williams, ITC 2002.
  42. IEEE Design Automation Conference, June 2002, New Orleans USA, Enhancing Test Efficiency for Delay Fault Testing Using Multiple-Clocked Schemes, Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, Ray Mercer and Tom Williams, DAC 2002.
  43. IEEE Design Automation Conference, June 2002, New Orleans USA, False-Path-Aware Statistical Timing Analysis and Efficient Path Selection for Delay Testing and Timing Validation, Jing-Jia Liou, Angela Krstic, Li-C. Wang and Kwang-Ting Cheng, DAC 2002.
  44. IEEE International Test Conference, Oct 2002, Atlanta USA, Delay Testing Considering Crosstalk-Induced Effects, Angela Krsti´c, Jing-Jia Liou, Yi-Min Jiang, and Kwang-Ting Cheng, International Test Conference (ITC) 2001.
  45. IEEE Design Automation Conference, June 2001, Las Vegas USA, Fast Statistical Timing Analysis By Probabilistic Event Propagation, Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, and Angela Krsti´c, Design Automation Conference (DAC) 2001.
  46. IEEE International Conference on Computer Aided Design, Nov 2000, San Jose USA, Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects, Jing-Jia Liou, Angela Krstic, Yi-Ming Jiang and Kwang-Ting Cheng, International Conference on Computer Aided Design (ICCAD) 2000.
  47. IEEE VLSI Test Symposium, April 2000, Montreal Canada, Path Selection For Delay Testing of Deep Sub-micron Devices Using Sensitivity Analysis, Jing-Jia Liou, Kwang-Ting Cheng, VLSI Test Symposium (VTS) 2000.
  48. IEEE Asia and South Pacific Design Automation Conference, January 2000, Yokohama Japan, Performance Sensitivity Analysis using Statistical Methods and Delay Testing, Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, and Sandip Kundu, Proceeding of Asian South Pacific Design Automation (ASP-DAC) 2000.

Journals

  1. T.-Y. Li, S.-Y. Huang, H.-J. Hsu, C.-W. Tzeng, C.-T. Huang, J.-J. Liou, H.-P. Ma, P.-C. Huang, J.-C. Bor, C.-C. Tien, C.-H. Wang and Cheng-Wen Wu, "AC-Plus Scan Methodology for Small Delay Testing and Characterization", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 21 Issue: 2 Pages: 329-341, Feb, 2013.
  2. Bor-Sen Chen, Chih-Yuan Hsu, and Jing-Jia Liou, "Robust Design of Biological Circuits: Evolutionary Systems Biology Approach, ", Applications of Synthetic Biology in Microbial Biotechnology, Volume 2011 (2011), Article ID 304236
  3. Jing-Jia Liou “Simulation and Extraction of Gene Regulatory Networks with Statistical Timing Models”, International Journal of Systems and Synthetic Biology, 1(1) June 2010, pp. 147-167.
  4. Chun-Yu Yang, Ying-Yen Chen, Sung-Yu Chen and Jing-Jia Liou, “Automatic Test Wrapper Synthesis for a Wireless ATE Platform”, IEEE Design and Test of Computers, May/June, 2010.
  5. Ying-Yen Chen and Jing-Jia Liou “Diagnosis Framework for Locating Failed Segments of Path Delay Faults, “ IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Volume: 16 Issue: 6 Pages: 755-765 June, 2008.
  6. Peng, Y.-L.; Wu, C.-W.; Liou, J.-J.; Huang, C.-T., “BIST-based diagnosis scheme for field programmable gate array interconnect delay faults,” IET Computers & Digital Techniques, Volume 1, Issue 6, Nov. 2007 Page(s):716 - 723
  7. Li-C. Wang, Jing-Jia Liou, and Kwang-Ting Cheng, "Critical Path Selection for Delay Fault Testing Based Upon a Statistical Timing Model," IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, Vol. 23, No. 11, November 2004.
  8. Liou, Jing-Jia; Krstic, Angela; Jiang, Yi-Ming; Cheng, Kwang-Ting, “Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v 22, n 6, June, 2003, p 756-769.
  9. Krstic, A.; Wang, L.-C.; Cheng, K.-T.; Liou, J.-J.; Abadir, M.S., “Delay defect diagnosis based upon a statistical timing model - The first step,” IEE Proceedings: Computers and Digital Techniques, v 150, n 5 SPEC. ISS., September, 2003, p 346-354.
  10. Liou JJ, Wang LC, Krstic A, Cheng KTT, “Critical path selection for deep sub-micron delay test and timing validation,” IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, v E86A (12): 3038-3048 DEC 2003.