-
K.-T.
Cheng, S.-Y. Huang, and W.-J. Dai,
"Fault
Emulation: A Novel Approach to Fault Grading", Proc.
Int'l Conf. on Computer-Aided Design, pp. 681-686, (Nov. 1995).
abstract
-
S.-Y.
Huang,
K.-T. Cheng, and K.-C. Chen,
"On
Verifying the Correctness of Retimed Circuits", Proc.
of Great-Lake Symposium on VLSI, pp. 277-281, (March 1996).
abstract
-
S.-Y.
Huang,
K.-C. Chen, K.-T. Cheng, and T.-C. Lee,
"Vector
Generation for Accurate Power Simulation", Proc.
of IEEE/ACM Design Automation Conf., pp. 161-164, (June. 1996).
abstract
-
S.-Y.
Huang,
K.-C. Chen, and K.-T. Cheng,
"Error
Correction Based on Verification Techniques", Proc.
of IEEE/ACM Design Automation Conf., pp. 258-261, (June. 1996).
abstract
-
S.-Y.
Huang,
K.-T. Cheng, K.-C. Chen, and T.-C. Lee,
"A
Novel Methodology for Transistor-level Power Simulation",
Int'l Symposium on Lower Power Electronic Design, pp. 67-72, (Aug.
1996). abstract
-
S.-Y.
Huang,
K.-T. Cheng and K.-C. Chen,
"An
ATPG-based Framework for Verifying Sequential Equivalence",
Proc. Int'l Test Conf., pp. 865-874, (Oct. 1996).
abstract
-
S.-Y.
Huang,
K.-T. Cheng and K.-C. Chen,
"AQUILA:
An Equivalence Verifier for Large Sequential Circuits",
Proc. of Asia and South Pacific Design Automation Conf., pp.
455-460, (Jan. 1997).
abstract
-
S.-Y.
Huang,
K.-C. Chen, and K.-T. Cheng,
"Incremental
Logic Rectification", Proc. of VLSI Test
Symposium, pp. 134-139, (April 1997).
abstract
-
S.-Y.
Huang,
K.-T. Cheng, K.-C. Chen, and D. I. Cheng, "ErrorTracer:
A Fault Simulation Based Approach to Design Error Diagnosis",
Proc. of Int'l Test Conf., pp. 974-981, (Nov. 1997).
-
Y.-M.
Jiang, S.-Y. Huang, K.-T. Cheng, D. C. Wang, and C.-Y. Ho, "A
Hybrid Power Model for RTL Power Estimation", Proc. of Asia and
South Pacific Design Automation Conf., pp. 551-556, (Feb. 1998).
-
S.-Y.
Huang,
K.-T. Cheng, and K.-C. Chen, "General
Design Error Diagnosis for Sequential Circuits",
Proc. of IEEE/ACM Design Automatic Conf., pp. 632-637, (June 1998).
-
Yi-Min
Jiang, S.-Y.
Huang, K.-T. Cheng, and D.-C. Wang, C.-Y. Ho, "A Hybrid Power
Model For RTL Power Estimation," Proc. of Asia and South Pacific
Design Automation Conf., pp. 551-556, (Feb. 1998).
-
S.-Y.
Huang
and D.-M. Kwai, "A
High-Speed Built-In Self-Test Design for DRAMs",
Proc. of Int'l Symposium on VLSI-TSA (Technology, Systems, and
Applications), pp. 50-53, (June 1999).
-
S.-Y.
Huang,
"On
Speeding Up Finite State Machines Using Catalyst Circuitry",
Proc. of Asia and South Pacific Design Automation Conf. (ASP-DAC),
583-588, (Jan. 2001).
-
S.-Y.
Huang,
"Towards
The Logic Defect Diagnosis For Partial-Scan Designs",
Proc. of Asia and South Pacific Design Automation Conf. (ASP-DAC),
pp. 313-318, (Jan. 2001).
-
S.-Y.
Huang,
"On
Improving the Accuracy of Multiple Defect Diagnosis",
Proc. of VLSI Test Symposium (VTS), pp. 34-39, (April 2001).
-
C.-J.
Liu and S.-Y. Huang, "Low-Power Synthesis For Extended Finite
State Machines," Proc. of 12th VLSI/CAD Symposium, Taiwan, (Aug. 2001).
-
C.-C.
Lu and S.-Y. Huang, "Improving the Accuracy of Mixed-Level
Power Estimation for CMOS Logic Circuits With Power Management,"
Proc. of 12th VLSI/CAD Symposium, Taiwan, (Aug. 2001).
-
H.-C.
Kao, M.-F. Tsai, S.-Y. Huang, C.-W. Wu, W.-F. Chang, and S.-K. Lu, "Efficient
Double Fault Diagnosis For CMOS Logic Circuits," Proc.
of 12th VLSI/CAD Symposium, Taiwan, (Aug. 2001).
-
C.-W. Wang, R.-S.
Tzeng, C.-F. Wu, C.-T. Huang, C.-W. Wu, S.-Y. Huang, S.-H. Lin, and
H.-P. Wang, "A Built-In Self-Test and Self-Diagnosis Scheme for
Heterogeneous SRAM Clusters," Proc. of Asian Test Symposium,
pp. 103-108, (Nov. 2001).
-
S.-Y.
Huang, "Speeding Up The Byzantine Fault Diagnosis Using Symbolic
Simulation," Proc. of VLSI Test Symposium, pp. 193-198, (April
2002).
-
Y.-C.
Tsai, S.-Y. Huang, C.-P. Su, C.-T. Huang, and C.-W. Wu, "Fine-Grain
Mixed-Level Power Estimation Based On Disparity Path Analysis,"
Proc. of 12th VLSI/CAD Symposium, Taiwan, (Aug.
2002).
-
H.-B.
Wang, S.-Y. Huang, and J.-R. Huang, "Gate-Delay
Fault Diagnosis Using The Inject-And-Evaluate Paradigm For Full-Scan
Designs", Proc. of Int'l Symposium on Defect and Fault
Tolerance in VLSI Systems (DFT'02), (Nov. 2002).
-
S.-Y.
Huang, "Diagnosis Of
Byzantine Open-Segment Faults," Proc. of Asian Test Symposium,
pp. 248-253, (Nov. 2002).
-
M.-L. Lee, T.-T.
Hwang, and S.-Y. Huang, "Decomposition of Extended Finite
State Machine For Low-Power Design," Proc. of Design Automation
and Test in Europe, pp. 1152-1153, (2003).
-
S.-K
Lu, J.-L. Chen, C.-W. Wu, K.-F. Chang, and S.-Y. Huang,
"Combinational Circuit Fault Diagnosis Using Logic Emulation,"
Proc.
of Int'l Symp. on Circuits and Systems, Vol. 5, pp. 549-552, May 2003.
-
S.-F.
Chen, Y.-J. Juang, S.-Y. Huang, and Y.-C. King, "Logarithmic
CMOS Image Sensor Through Multi-Resolution Analog-To-Digital Conversion,"
Proc. of Int'l Symposium on VLSI Technology, Systems, and
Applications, pp. 227-230, (April 2003).
-
Y.-T. Lin and S.-Y.
Huang, "Efficient Bit-Oriented Implementation of FIR Filters
Using A New Compressor,"
Proc.
of Int'l SOC Conf., pp.269-271, (Sept. 2003).
-
B.-R.
Lin, S.-Y. Huang, C.-H. Lai, and Y.-C. King, "A High Dynamic
Range CMOS Image Sensor Design Based On Two-Frame Composition,"
Proc.
of Int'l SOC Conf., pp. 389-392, (Sept. 2003).
-
Y.-C.
Lin and S.-Y. Huang, "Chip-Level
Diagnostic Strategy For Full-Scan Designs With Multiple Faults,"
Proc.
of Asian Test Symposium, pp. 38-44, (Nov. 2003).
(Invited)
-
S.-Y. Huang, "A
Fading Algorithm For Sequential Fault Diagnosis," to
appear in Proc.
of In'l Symposium on Defect and Fault Tolerance on VLSI Systems, pp.
139-147, (Nov.
2004).
-
K.-H.
Lai, S.-Y. Huang, P.-C. Chiang, "A Sizing Methodology For A
Low-Noise Comparator,"
Proc.
of Asia-Pacific Conf. on Circuits and Systems, pp. 253-256, (Dec. 2004).
-
M.-Y.
Sum, S.-Y. Huang, C.-C. Weng, and K.-S. Chang, "Accurate RT-Level
Power Estimation Using Up-Down Encoding,"
Proc.
of Asia-Pacific Conf. on Circuits and Systems, pp. 69-72, (Dec. 2004).
-
Y.-F.
Lee, S.-Y. Huang, S.-Y. Hsu, I.-L. Chen, C.-T. Shieh, J.-C. Lin,
S.-C. Chang, "Power Estimation Strategies For A Low-Power Security
Processor," Proc. of Asia-Pacific Design Automation Conf.
(ASP-DAC),
pp. 367-371, (Jan.
2005).
-
M.-Y.
Sum, K.-S. Chang, C.-C. Weng, and S.-Y. Huang, "ToggleFinder:
Accurate RTL Power Estimation For Large Designs," Int'l
Symposium on VLSI Design, Automation, and Test, (VLSI-DAT), pp. 16-19,
(April
2005).
-
S.-P.
Cheng and S.-Y. Huang, "A Low-Power SRAM Design Using Quiet-Bitline
Architecture," Proc. of IEEE Int'l Workshop on Memory
Technology, Design, and Testing, (MTDT), (Aug. 2005).
-
J.-S.
Yang and S.-Y. Huang, "Quick Scan Chain Diagnosis Using Signal
Profiling," Proc. of Int'l Conf. on Computer Design, (ICCD),
(Oct. 2005).
-
K.-S.
Chang, C.-C. Weng, and S.-Y. Huang, "Accurate RTL Power
Estimation for a Security Processor," Emerging Information
Technology Conf., 2005.
-
L.-Y.
Ko, S.-Y. Huang, J.-J. Chiou, and H.-C. Cheng, "Modeling and
Testing of Intra-Cell Bridging Defects Using Butterfly Structure,"
Proc.
of VLSI Design, Automation, and Testing (VLSI-DAT), pp. 159-162, (April 2006).
(Best Presentation Award)
-
J.-J.
Hsu, S.-Y. Huang, and C.W. Tzeng, "A New Robust Paradigm for
Diagnosing Hold-Time Faults in Scan Chains," Proc. of VLSI Design,
Automation, and Testing (VLSI-DAT), pp. 171-174, (April 2006).
-
C.-W.
Wu, C.-T. Huang, S.-Y. Huang, P.-C. Huang, T.-Y. Chang, and Y.-T.
Hsing, "The HOY Tester - Can IC Testing Go
Wireless," Proc. of VLSI Design,
Automation, and Testing (VLSI-DAT), pp. 183-186, (April 2006).
-
Y.-C.
Lai and S.-Y. Huang, "X-Calibration: A Wide-Range Leakage
Current Cancellation Technique for Nanometer SRAM Designs," Proc.
of Int'l SoC Design Conf., (Oct. 2006).
-
C.-C.
Weng C.-S. Yang, and S.-Y. Huang, "RT-Level Vector
Selection for Realistic Peak Power Simulation", pp. 576-581,
Proc.
of Great Lakes Symp. on VLSI, (March 2007).
-
H.-J.
Hsu, C.-C. Tu, and S.-Y. Huang, "Built-In Speed Grading with a
Process Tolerant ADPLL", Proc. of Asian Test
Symposium, pp. 384-390, (Oct. 2007).
-
Y-C.
Lai and S.-Y. Huang, "Resilient SRAM Design Using BIST-Assisted
Timing Tracking," Proc. of Memory Technology, Design, and Testing
Workshop, pp. 39-41, (Dec. 2007).
-
H.-J.
Hsu, C.-C. Tu, and S.-Y. Huang, "A
High-Resolution All-Digital Phase-Locked Loop with Its Application to
Built-In Speed Grading for Memory," Proc. of Int'l Symp. on VLSI
Design, Automation, and Testing, pp. 267-270, (April 2008).
-
C.-W.
Tzeng and S.-Y. Huang, "Two-Gear Lower-Power Scan
Test," Proc. of Asian Test Symposium,
pp. 337-342, (Nov. 2008).
-
C.-W.
Tzeng and S.-Y. Huang, "QC-Fill: An X-Fill Method for Quick-and-Cool
Scan Test," Proc. of Design Automation and Test in
Europe (DATE), pp. 1142-1147, (April 2009).
-
C.-W.
Tzeng, C.-Y. Lin, S.-Y. Huang, C.-T. Huang, J.-J. Liou, H.-P. Ma,
P.-C. Huang, and C.-W. Wu, "iScan: Indirect-Access Scan Test over HOY
Test Platform," in Proc. of Int'l Symp. on VLSI
Design, Automation, and Testing, (VLSI-DAT), pp. 60-63, (April 2009).
-
H.-J.
Hsu and S.-Y. Huang, "An Low-Jitter All-Digital
Phased-Locked Loop Using a Suppressive Digital Loop Filter,"
Proc. of Int'l Symp. on VLSI
Design, Automation, and Testing, (VLSI-DAT), pp. 60-63, (April 2009).
-
C.-W.
Tzeng and S.-Y. Huang, "Use of Multicasting-Scan Architectures
for Compound Defect Diagnosis," Proc. of IEEE
Circuits and Systems Int'l Conf. on Testing and Diagnosis, pp. 1-4, (April
2009).
-
C.-W. Tseng and
S.-Y. Huang, "Output
Test Compression for Compound Defect Diagnosis," Proc. of
IEEE Conf. on ASIC, pp. 569-572, (2009).
-
C.-W.
Hsu, J.-J. Lia, J.-C. Yeh, J.-J. Chen, S.-Y. Huang, and J.-J. Liou,
"Memory-Aware Power Modeling for PAC DSP Core,"
Proc. of IEEE Asian Symp. on Quality Electronics Design,
(ASQED), pp. 319-324, (July 2009).
-
Y.-Y.
Chen and S.-Y. Huang, "Rapid and
Accurate Timing Modeling for SRAM Compiler,"
Proc. of
IEEE Int'l Workshop on Memory
Technology, Design, and Testing, (MTDT), pp. 73-76, (Nov. 2009).
-
W.-T. Hsieh,
J.-C. Yeh, and S.-Y. Huang, "PAC Duo System
Power Estimation at ESL," Proc. of IEEE Asia and South Pacific
Design Automation Conf., pp. 815-820, (Jan. 2010).
-
C.-Y. Lin, P.-Y.
Chen, C.-K. Tseng, C.-W. Huang, C.-C. Weng, C.-B. Kuan, S.-H. Lin, S.-Y.
Huang, and J.-K. Lee, "Power Aware SID-Based
Simulator for Embedded Multicore DSP SubSystems," Proc. of
Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp.
95-103, (2010).
-
T.-Y. Li, S.-Y. Huang, H.-J. Hsu, C.-W. Tzeng, C.-T. Huang, J.-J. Liou, H.-P. Ma,
P.-C. Huang, J.-C. Bor, C.-C. Tien, M. Wang, and C.-W. Wu, "AF-Test:
Adaptive-Frequency Scan Test Methodology for Small-Delay Defects,"
Proc. of IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems
(DFT), pp. pp. 340-348, Kyoto, Japan, (Sept. 2010).
-
J.-W. You, S.-Y. Huang, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, "Performance
Characterization of TSV in 3D IC via Sensitivity Analysis," Proc. of Asian Test Symposium
(ATS),
pp. 389-394, (Dec. 2010).
-
J.-W. Ke, S.-Y. Huang, and D.-M. Kwai, "A High-Resolution
All-Digital Duty- Cycle Corrector With a New Pulse-Width Detector,"
Proc. of Electron Devices and Solid-State Circuits (EDSSC),
pp. 1-4, (Dec. 2010).
-
C.-K. Tseng,
S.-Y. Huang, C.-C. Weng, S.-C. Fang, and J.-J. Chen, "Black-Box Leakage Power Modeling
for Cell Library and SRAM Compiler," Proc. of IEEE
Conf. on Design, Automation, and Test in Europe (DATE), pp. 1-6, (March 2011).
-
P.-Y. Chao, C.-W. Tzeng, S.-C. Fang, C.-C. Weng, and
S.-Y. Huang,
"Low-Jitter Code-Jumping for All-Digital PLL to Support Almost Continuous
Frequency Tracking," Proc. of Int'l Symp. on VLSI
Design, Automation, and Testing, (VLSI-DAT),
pp. 1-4, (April 2011).
-
S.-C. Fang, C.-C. Weng, C.-K. Tseng, C.-W. Hsu, J.-L. Liao,
S.-Y. Huang,
C.-L. Lung, and D.-M. Kwai, "SoC Power Analysis
Framework and Its Application to Power-Thermal Co-Simulation,"
Proc. of VLSI Design, Automation, and Test (VLSI-DAT), pp. 1-4,
(2011).
-
C.-W. Hsu, J.-L. Liao, S.-C. Fang, C.-C. Weng,
S.-Y. Huang, W.-T.
Hsieh, and J.-C. Yeh, "PowerDepot: Integrating IP-Based Power Modeling with
ESL Power Analysis for Multi-Core SoC Designs," Proc.
of Design
Automation Conf. (DAC), pp. 47-52, (2011).
-
C.-F. Li, C.-Y. Lee, C.-H. Wang, S.-L. Chang, L.-M. Deng, C.-C. Chi, H.-J.
Hsu, M.-Y. Chu, J.-J. Liou, S.-Y. Huang, P.-C. Huang, H.-P. Ma, J.-C. Bor,
C.-W. Wu, C.-C. Tien, C.-H. Wang, Y.-S. Kuo, C.-T. Huang, and T.-Y. Chang, "A
Low-Cost Wireless Interface with No External Antenna and Crystal Oscillator
for Cm-Range Contactless Testing," Proc.
of Design
Automation Conf. (DAC), pp. 771-776, (2011).
-
Y.-C. Chang,
S.-Y. Huang, C.-W. Tzeng, "A Fully
Cell-Based Design for Timing Measurement of Memory," Proc. of Int'l Test
Conf,
(ITC), pp. 1-10, (Nov. 2011).
-
R.-T. Ding, S.-Y. Huang, C.-W. Tzeng, S.-C. Fang, and C.-C. Weng, "Cyclic-MPCG:
Process-Resilient and Super-Resolution Multi-Phase Clock Generation by
Exploiting the Cyclic Property," Proc. of IEEE VLSI Design, Automation, and Test
(VLSI-DAT), pp. 1-4, (Apirl 2012).
-
Y.-H. Lin, S.-Y. Huang, K.-H. Tsai, W.-T. Cheng, S. Sunter, Y.-F.
Chou, and D.-M. Kwai, "Small Delay Testing for TSVs in
3D ICs", Proc. of IEEE Design Automation Conf. (DAC),
pp. 1031-1036, (June 2012).
-
C.-M. Lai, K.-W. Tan, L.-Y. Yu, Y.-J. Chen, J.-W. Huang, S.-C. Lai, F.-H.
Chung, C.-F. Yen, J.-M Wu, P.-C. Huang, K.-J. Chang, S.-Y. Huang, and
T.-S. Chu, "A UWB IR Timed-Array Radar Using Time-Shifted Direct-Sampling
Architecture," Proc. of IEEE VLSI Circuit Symp., pp. 54-55, (2012).
-
Y.-H. Lin, S.-Y. Huang, K.-H. Tsai, W.-T. Cheng, and S. Sunter, "A
Unified Method for Parametric Fault Characterization of Post-Bond TSVs",
Proc. of IEEE Int'l Test Conf. (ITC), Paper 12.1, pp. 1-10, (Nov. 2012).
-
Y.-H. Lin,
S.-Y. Huang,K.-H. Tsai, and W.-T. Cheng, "Programmable
Leakage Test and Binning for TSVs",
Proc. of IEEE Asian Test Symp. (ATS), pp. 43-48, (Nov. 2012).
-
C.-H. Hsu,
S.-Y. Huang, D.-M. Kwai, and Y.-F. Chou, "Worst-Case IR-Drop
Monitoring with 1GHz Sampling Rate," IEEE Proc. of VLSI Design, Automation, and Test (VLSI-DAT), pp.
1-4, (April 2013).
(Best Paper Award)
-
S.-Y. Huang, J.-Y. Lee, K.-H. (Hans) Tsai, and W.-T. Cheng, "At-Speed
BIST for Interposer Wires Supporting On-the-Spot Diagnosis", Int'l On-Line Test Symp. (IOLTS),
pp. 67-72, (July 2013).
-
S.-Y. Huang, L.-R. Huang, K.-H. (Hans) Tsai, and W.-T. Cheng, "Delay
Testing and Characterization of Post-Bond Interposer Wires in 2.5-D ICs",
Int'l Test Conf. (ITC), pp. 476-488, (Sept. 2013).
-
L.-R. Huang,
S.-Y. Huang, K.-H. (Hans) Tsai, W.-T. Cheng, and S. Sunter, "Mid-Bond
Interposer Wire Test",
Int'l Asian Test Symp. (ATS), pp. 153-158, (Nov. 2013).
-
S.-Y. Huang, Z.-F. Zeng, K.-H. (Hans) Tsai, and W.-T. Cheng, "On-the-Fly
Timing-Aware Built-In Self-Repair for High-Speed Interposer Wires in 2.5-D
ICs",
Proc. of IEEE
European Test Symp. (ETS), pp. 1-2, (May 2014).
-
S.-Y. Huang, H.-X. Li, Z.-F. Zeng,
K.-H. Tsai, and W.-T. Cheng, "On-Line Transition-Time
Monitoring for Die-to-Die Interconnects in 3D ICs", Proc. of Asian
Test Symp. (ATS), pp. 162-167, (Nov. 2014)
(Best Paper Award)
-
S.-Y. Huang, M.-T. Tsai, K.-H.
Tsai, and W.-T. Cheng, "Feedback-Bus Oscillation Ring:
A General Architecture for Delay Characterization and Test of Interconnects",
Proc. of Design, Automation, and Test in Europe (DATE), pp. 924-927, (March 2015).
-
S.-T. Tseng, Y.-H. Kao, C.-C. Peng, J.-Y.
Liu, S.-C. Chu, G.-F. Hong, C.-H. Hsieh, K.-T. Hsu, W.-T. Liu, Y.-H. Huang,
S.-Y. Huang, and T.-S. Chu, "A 65nm CMOS Low
Power Impulse Radar for Respiratory Feature Extraction," Proc. of
IEEE RFIC Symp., pp. 251-254, (May 2015).
-
H.-X. Li, H.-C. Fu,
S.-Y. Huang, J.-C. Jiang, D.-M. Kwai, and Y.-F. Chou, "Testing
Power-Delivery TSVs", Proc. of Asian Symp. on Quality Electronic
Design, pp. 127-131, (Aug. 2015).
-
H.-C. Fu, S.-Y. Huang, D.-M. Kwai,
and Y.-F. Chou, "Temperature-Aware Online Testing of
Power-Delivery TSVs," Proc. of IEEE Int'l 3D System Integration
Conf., TS10.3.1 - TS10.3.6, (Sept. 2015).
-
M.-T. Tsai, S.-Y. Huang, K.-H. (Hans)
Tsai, and W.-T. Cheng, "Monitoring the Delay of Long
Interconnects via Distributed TDC," Proc. of IEEE Int'l Test Conf.
(ITC),
(Oct. 2015).
-
J.-Y. Liu, S.-Y. Huang, T.-S. Chu, "Cell-Based
Programmable Phase-Shifter Design for Pulsed Radar SoC", Proc. of IEEE Int'l Conf. on ASIC,
pp. 1-4, (Nov. 2015).
(Invited)
-
Y.-J. Liao and S.-Y. Huang, "Temperature
Tracking Scheme for Programmable Phase-Shifter in Pulsed Radar SoC",
Proc. of IEEE Symp. on VLSI Design, Automation, and Test (VLSI-DAT), pp.
1-4, (April 2016).
-
S.-F. Yang, S.-Y. Huang, K.-H. (Hans)
Tsai, and W.-T. Cheng, "Testing of Small Delay Faults
in a Clock Network," Proc. of IEEE European Test Symp. (ETS),
pp. 1-6, (May 2016).
-
S.-Y. Huang, T.-H. Huang, K.-H.
Tsai, and W.-T. Cheng, "A Wide-Range Clock Signal
Generation Scheme for Speed Grading of a Logic Core," Proc.
of Int'l Conf. on High-Performance Computing & Simulation (HPCS), pp. 125-129, (July 2016).
-
P.-C. Huang, S.-Y.
Huang, "Cell-Based Delay Locked Loop Compiler,"
pp. 91-92, Proc. of Int'l SoC Design Conf., pp. 91-92, (Oct.
2016).
-
C.-C. Zheng, S.-Y. Huang, S.-K.
Lu, T.-C. Wang, K.-H.
Tsai, and W.-T. Cheng, "Online Slack-Time Binning
for IO-Registered Die-to-Die Interconnects," Proc. of IEEE
Int'l Test Conf. (ITC), pp. 1-8, (Nov. 2016).
-
S.-Y. Huang, C.-C. Zheng, "Die-to-Die
Clock Skew Characterization and Tuning for 2.5D ICs," Proc.
of IEEE Asian Test Symp. (ATS), Hiroshima, Japan, pp. 221-226, (Nov. 2016).
-
S.-Y. Huang, "Pre-bond
and Post-bond Testing of TSVs and Die-to-Die Interconnects",
Proc. of IEEE Asian Test Symp., Hiroshima, Japan, pp. 80-85, (Nov.
2016). (Invited)
-
S.-Y. Huang, "Test
Strategies for the Clock and Power Distribution Networks in a Multi-Die
IC",
Proc. of IEEE Symp. on VLSI Design, Automation, and Test
(VLSI-DAT), pp. 1-2, (April 2017). (Invited)
-
C.-H. Wu, S.-Y.
Huang, M. Chern, Y.-F. Chou, and D.-M. Kwai, "A
Resilient Cell-Based Architecture for Time-to-Digital Converter",
Proc. of IEEE Int'l Symp. on VLSI (IS-VLSI), pp. 7-12, Bochum, Germany,
pp. 7-12, (July 2017).
-
C.-Y. Cheng, S.-Y.
Huang, D.-M. Kwai, and Y.-F. Chou, "DLL-Assisted
Clock Synchronization Method for Multi-Die ICs", Proc. of IEEE
Int'l Conf. on Computer Design (ICCD), Boston, USA, pp. 473-476, (Nov. 2017).
-
G.-H. Lian, S.-Y.
Huang, and W.-Y. Chen, "Cloud-Based PVT
Monitoring System for IoT Devices,"
Proc. of IEEE Asian Test Symp. (ATS), Taipei, Taiwan, pp. 76-81, (Nov.
2017).
-
C.-H. Wu, S.-Y.
Huang, Y.-F. Chou, and D.-M. Kwai, "Time-to-Digital
Converter Compiler for Dynamic Voltage Drop Monitoring",
IEEE Workshop on RTL and High-Level Testing (WRTLT), (Nov. 2017).
(Best Paper Award)
-
C.-E. Lee and
S.-Y. Huang, "A Cell-Based Fractional-N
Phase-Locked Loop Compiler," Proc. of IEEE Int'l Conf. on
Synthesis, Modeling, Analysis, and Simulation Methods and Applications
to Circuit Design (SMACD), pp. 273-276, (July 2018).
-
Yu-Chi Wei and
S.-Y. Huang, "A Folded Locking Scheme
for the Long-Range Delay Block in a Wide-Range DLL", Proc. of IEEE
Int'l SOC Design Conf, (ISOCC), pp. 90-91, (Nov. 2018).
(Best Paper Award - DB
HiTek Award)
-
M. Chern, S.-W. Lee,
S.-Y. Huang, Y. Huang, G. Veda, K.-H. Tsai, and W.-T. Cheng, "Improving
Scan Chain Diagnostic Accuracy
Using Multi-Stage Artificial Neural
Networks", Proc. of IEEE Asian-Pacific
Design Automation Conf, (ASP-DAC), (Jan. 2019).
-
Z.-H. Zhang, W. Chu, and S.-Y. Huang,
"The Ping-Pong Tunable Delay Line in A Super-Resilient Delay-Locked
Loop," Proc. of IEEE Design Automation Conf.
(DAC), (June 2019).
-
W. Chu and S.-Y. Huang, "A
Cell-Based Wide-Frequency-Range DLL Supporting Fast Frequency Scaling,"
Proc. of
IEEE
Int'l NEWCAS Conf., (June 2019).
-
W. Chu and S.-Y. Huang, "Online
Testing of Clock Delay Faults in a Clock Network," Proc. of
IEEE
Int'l Test Conf.
in Asia, (ITC-Asia), pp. 163-168, (Sept. 2019).
-
W. Chu and S-.Y. Huang,
"Overall Strategy for Online Clock System Checking
Supporting Heterogeneous Integration", Proc. of
IEEE
Int'l Test Conf., (ITC),
at Washington DC, pp. 1-10, (Nov. 2019).
-
W Chu, W.-H. Chen, and S.-Y. Huang,
"Duty-Cycle Correction For a Super-Wide Frequency Range from 10MHz to 1.2GHz",
Proc. of
IEEE
Int'l Conf. on Computer
Design (ICCD), pp. 457-460, (Oct. 2020).
-
D. Lin, J.-Y. Yang, S.-Y. Huang, "A
Voting Phase Detector Design with Mitigated Process Variation",
Proc. of
IEEE
Int'l SoC Design Conf. (ISOCC), pp. 91-92,
(Oct. 2020).
-
W.-H. Chen, C.-C. Hsu, and S.-Y. Huang,
"Rapid PLL Monitoring By a Novel min-MAX Time-to-Digital
Converter", Proc. of
IEEE
Int'l Test
Conf., (ITC) @Washington DC, pp. 1-8, (Nov. 2020).
-
S.-Y. Huang, "Overview
of On-Chip Performance Monitors for Clock Signals", Proc. of
IEEE
Asian Test Symp. (ATS),
pp. 1-4, (Nov. 2020).
(Invited)
-
J.-Y. Yang and S.-Y. Huang, "Fault
and Soft Error Tolerant Delay-Locked Loop", Proc. of
IEEE
Asian Test Symp. (ATS),
pp. 1-6, (Nov. 2020).
-
C.-L. Tsai, W.-H. Chen, and S.-Y. Huang, "A
Duty-Cycle Monitor Supporting A Wide Frequency Range of Clock Signal",
Proc. of IEEE Int'l Test Conf. in Asia
(ITC-Asia), (Aug. 2021).
-
Y.-H. Lee and S.-Y. Huang, "Rigorous
Test Flow for PLL
to Identify Weak Devices",
IEEE Int'l Test Conf.
in Asia (ITC-Asia), (Aug. 2021).
-
C.-L. Tsai and S.-Y. Huang,
"Just-Enough Stress Test for
Infant-Mortality Screening Using Speed Binning", Proc. of
IEEE
Int'l Test
Conf., (ITC) @Anaheim, pp. 1-8, (Sept. 2022).
-
Y.-C. Su and S-.Y. Huang, "Just-Enough
Strategy for Accurate Clock Jitter Measurement Using A Cyclic
Time-to-Digital Converter", Proc. of Int'l SoC
Design Conf., (Oct. 2022).
-
Y.-S. Wang, H.-K. Teng, and S.-Y. Huang,
“Optimization of DCO Using Latch-Based Varactor
Cells for a Cell-Based PLL”, Proc. of IEEE Midwest Symp.
on Circuits and Systems, (Aug. 2023).
-
Y.-H. Lee, W.-H.
Chen, and S.-Y. Huang, "Self-Sufficient
Clock Jitter Measurement Methodology Using Dithering-Based Calibration",
Proc. of IEEE Int'l Test Conf.
in Asia (ITC-Asia), (Sept. 2023).
-
C.-L. Tsai and S.-Y. Huang, "Trustworthy
Lifetime Prediction by Aging History Analysis and Multi-Level Stress
Test", Proc.
of IEEE Int'l Test Conf.
in Asia (ITC-Asia), (Sept. 2023).
-
O.-D. Lin and S.-Y. Huang, "Cell-Based
Aging Sensor Using Built-In Speed Grading",
Proc.
of IEEE Nordic Circuits
and Systems Conf., (Nov. 2023).