Publications

Journal Papers

Conference Papers

Invited Conference Talks and Papers

Patents

Book Chapters and others

 

Journal Papers (期刊論文)

          (* Corresponding author)

1.     Bohan Lin;Yachuan Pang;Bin Gao;Jianshi Tang;Dong Wu;Ting-Wei Chang;Wei-En Lin;Xiaoyu Sun;Shimeng Yu;Meng-Fan Chang;He Qian;Huaqiang Wu, “A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source,” IEEE Journal of Solid-State Circuits (JSSC), vol.XX, No. x, pp. xxx-xxx, XX 2021 (accepted)

2.     Tzu-Hsiang Hsu;Yi-Ren Chen;Ren-Shuo Liu;Chung-Chuan Lo;Kea-Tiong Tang;Meng-Fan Chang;Chih-Cheng Hsieh, “A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction,” IEEE Journal of Solid-State Circuits (JSSC), vol.XX, No. x, pp. xxx-xxx, XX 2021 (accepted)

3.     Jinshan Yue, Yongpan Liu, Ruoyang Liu, Wenyu Sun, Zhe Yuan, Yung-Ning Tu, Yi-Ju Chen, Ao Ren, Yanzhi Wang, Meng-Fan Chang, Xueqing Li, Huazhong Yang, “STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration,” IEEE Journal of Solid-State Circuits (JSSC), vol.XX, No. x, pp. xxx-xxx, XX 2021 (accepted)

4.     Cheng-Xin Xue, Yen-Cheng Chiu, Ta-Wei Liu, Tsung-Yuan Huang, Je-Syu Liu, Ting-Wei Chang, Hui-Yao Kao, Jing-Hong Wang, Shih-Ying Wei, Chun-Ying Lee , Sheng-Po Huang, Je-Min Hung, Shih-Hsih Teng, Wei-Chen Wei, Yi-Ren Chen , Tzu-Hsiang Hsu, Yen-Kai Chen , Yun-Chen Lo, Tai-Hsing Wen1 , Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang , Mon-Shu Ho, Chin-Yi Su , Chung-Cheng Chou, Yu-Der Chih and Meng-Fan Chang*, “A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices,” Nature Electronics, vol. 4, pp.81-90, Jan. 2021 (Research Article)

5.     Yue Xi, Bin Gao, Jianshi Tang, An Chen, Meng-Fan Chang, Xiaobo Sharon Hu, Jan Van Der Spiegel, He Qian, Huaqiang Wu, “In-memory Learning with Analog Resistive Switching Memory: A Review and Perspective,” Proceedings of the IEEE, vo. 109, no. 1, 2021

6.     Yen-Cheng Chiu, Zhixiao Zhang, Jia-Jing Chen;Xin Si, Ruhui Liu, Yung-Ning Tu, Jian-Wei Su, Wei-Hsing Huang, Jing-Hong Wang, Wei-Chen Wei, Je-Min Hung, Shyh-Shyuan Sheu, Sih-Han Li, Chih-I Wu, Ren-Shuo Liu;Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang*, “A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors,” IEEE Journal of Solid-State Circuits (JSSC), vol. 55, No. 10, pp. 2790-2800, Oct. 2020

7.     Wenqiang Zhang, Bin Gao, Jianshi Tang, Peng Yao, Shimeng Yu, Meng-Fan Chang, Hoi-Jun Yoo, He Qian, Huaqiang Wu, “Neuro-inspired computing chips,” Nature Electronics, vol. 3, pp.371-382, July 2020 (Review Article)

8.     Wei-Chen Wei, Chuan-Jia Jhang, Yi-Ren Chen, Cheng-Xin Xue, Syuan-Hao Sie, Jye-Luen Lee, Hao-Wen Kuo, Chih-Cheng Lu, Meng-Fan Chang, Kea-Tiong Tang,“A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random-Access Memory (ReRAM)-based Computing-In-Memory,”IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 6,  no. 1, pp. 45-52, July 2020

9.     Je-Min Hung, Xueqing Li, Juejian Wu, and Meng-Fan Chang*, “Challenges and Trends in Developing Nonvolatile Memory-Enabled Computing Chips for Intelligent Edge Devices,” IEEE Transactions on Electron Devices (TED), vol 67 issue 4, pp.1444-1453, April 2020

10.  C.-X. Xue..., M.-F. Chang* “Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors.” IEEE Journal of Solid-State Circuits (JSSC), vol.55, No. 1, pp.203-215, Jan. 2020

11.  X. Si..., M.-F. Chang* “A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors.” IEEE Journal of Solid-State Circuits (JSSC), vol.55, No. 1, pp.189-202, Jan. 2020

12.   X. Si..., M.-F. Chang* “A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro with Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors.” IEEE Transactions on Circuits and System–I: Regular Papers (TCAS-I), vol.66, No. 11, pp.4172-4185, Nov. 2019

13.   Zhixiao Zhang, Xin Si, Srivatsa Srinivasa, Akshay Krishna Ramanathan, Meng-Fan Chang*, “Recent Advances in Compute-in-Memory Support for SRAM Using Monolithic 3-D Integration.” IEEE Micro, vol.39, No. 6, pp.28-37, Nov. 2019

14.  C.-X. Xue..., M.-F. Chang* “A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier.” IEEE Journal of Solid-State Circuits (JSSC), vol.54, No. 10, pp.2743-2753, Oct. 2019

15.  W.-H. Chen..., M.-F. Chang* “CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors.” Nature Electronics, vol. 2, No. 9, pp.420-428, Sep. 2019 (Research Article)

16.  B. Yan..., M.-F. Chang*, Y. Chen*, and H. Li*, “Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives.” Wiley Online Library: Advanced Intelligent Systems, vol. 1, No. 7, pp. 1900068 1 16 , Aug 2019

17. Srivatsa Srinivasa, Akshay Krishna Ramanathan, Xueqing Li, Wei-Hao Chen, Sumeet Kumar Gupta, Meng-Fan Chang, Swaroop Ghosh, Jack Sampson, Vijaykrishnan Narayanan,  “ROBIN: Monolithic-3D SRAM for Enhanced Robustness With In-MemoryComputation Support”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.66, No. 7, pp.2533-2545, July 2019
18. Yiming Wang, Yun Li, Haihua Shen, Dongyu Fan,  Dongyu Fan,  Wei Wang   ,   Ling Li, Qi Liu,  Feng Zhang,  Xinghua Wang,  Meng-fan Chang, Ming Liu , “A Few-Step and Low-Cost Memristor Logic based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 4, 662-666, April 2019
19. Chieh-Pu Lo, Wen-Zhang Lin, Wei-Yu Lin, Huan-Ting Lin, Tzu-Hsien Yang, Yen-Ning Chiang, Ya-Chin King, Chrong-Jung Lin, Yu-Der Chih, Tsung-Yung Jonathon Chang, and Meng-Fan Chang*, ” A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme against Resistance and Write-Delay Variation,” IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 2, 584-595, Feb. 2019
20. He Zhang, Wang Kang, Youguang Zhang, Meng-Fan Chang, Weisheng Zhao*, “A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM ,” IEEE Access, pp.64250-64260, Oct. 2018
21. Ting-I Chou,     Kwuang-Han Chang,     Jia-Yin Jhang,    Shih-Wen Chiu,     Guoxing Wang,     Chia-Hsiang Yang,     Herming Chiueh,     Hsin Chen,     Chih-Cheng Hsieh,     Meng-Fan Chang,     Kea-Tiong Tang*, “A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65,  no. 10, Page s: 1365- 1369, Oct. 2018.    
22. Wei-Hao Chen, Chien-Fu Chen, Yi-Ju Chen, Hsiao-Yun Chiu, Chang-Hong Shen, Jia-Min Shieh, Fu-Kuo Hsueh, Chih-Chao Yang, Bo-Yuan Chen, Guo-Wei Huang, Kai-Shin Li, Wen-Kuan Yeh, Hiroyuki Yamauchi, Meng-Fan Chang*, “  A Dual-Split-Controlled 4P2N 6T SRAM in Monolithic 3D-ICs With Enhanced Read Speed and Cell Stability for IoT Applications ,”  IEEE Electron Device Letters, vol. 39. No. 8, pp. 1167- 1170, Aug. 2018.
23. Xueqing Li,     Sumitha George,     Yuhua Liang,     Kaisheng Ma,     Kai Ni,     Ahmedullah Aziz,    Sumeet Kumar Gupta,    John Sampson,     Meng-Fan Chang,     Yongpan Liu,    Huazhong Yang,     Suman Datta,     Vijaykrishnan Narayanan, “  Lowering Area Overheads for FeFET-Based Energy-Efficient Nonvolatile Flip-Flops,”  IEEE Transactions on Electron Devices, Volume: 65   ,  Issue: 6, Page s: 2670  -  2674, June 2018
24. Srivatsa Srinivasa;   Xueqing Li,   Meng-Fan Chang,   John Sampson,   Sumeet Kumar Gupta,  Vijaykrishnan Narayanan, “Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Vol. 26, no. 4, pp.671-683, April 2018
25. Albert Lee,   Hochul Lee,   Farbod Ebrahimi,,  Bonnie Lam,   Wei-Hao Chen,   Meng-Fan Chang,   Pedram Khalili Amiri,  Kang-L. Wang, “A Dual-Data Line Read Scheme for High-Speed Low-Energy Resistive Nonvolatile Memories,”  IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Vol. 26, 272-279, Feb. 2018

26.  Hsiang-Jen Tsai,  Chien-Chih Chen, Yin-Chi Peng, Ya-Han Tsao;   Yen-Ning Chiang,  Wei-Cheng Zhao,  Meng-Fan Chang,  Tien-Fu Chen, “A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous Discrete Finite Automata,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25 ,  no. 12, pp. 3302-3316, Dec. 2017

27. Xueqing Li, Sumitha George, Kaisheng Ma, Wei-Yu Tsai, Ahmedullah Aziz,   John Sampson,  Sumeet Kumar Gupta,  Meng-Fan Chang, Yongpan Liu,  Suman Datta, Vijaykrishnan Narayanan, “Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops,” IEEE Transactions on Circuits and Systems I: Regular Papers,   vol. 64, issue 11, pp. 2907-2919, Nov. 2017
28. Xiaoyu Sun;   Rui Liu;   Yi-Ju Chen;   Hsiao-Yun Chiu;   Wei-Hao Chen;   Meng-Fan Chang;   Shimeng Yu, “Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, issue 10, 2962-2965, Oct. 2017

29.  Zhibo Wang;   Yongpan Liu;   Albert Lee;   Fang Su;   Chieh-Pu Lo;   Zhe Yuan;   Jinyang Li;   Chien-Chen Lin;   Wei-Hao Chen;   Hsiao-Yun Chiu;   Wei-En Lin;   Ya-Chin King;   Chrong-Jung Lin;   Pedram Khalili Amiri;   Kang-Lung Wang;   Meng-Fan Chang;   Huazhong Yang, “A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving >4x Faster Clock Frequency and >6x Higher Restore Speed,” IEEE Journal of Solid-State Circuits (JSSC), vol. 52, no. 10, 2769-2785, Oct. 2017

30. Yongpan Liu, ...Meng-Fan Chang, Huazhong Yang, “Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 10, pp. 1660-1673, Oct. 2017
31. Meng-Fan Chang*, et al.,” A Compact-Area Low-VDDmin 6T SRAM with Improvement in Cell Stability, Read-Speed and Write-Margin Using a Dual-Split-Control Assist Scheme,” IEEE Journal of Solid-State Circuits (JSSC), vol. 52, no. 9, pp. 2498-2514, Sept. 2017
32. Albert Lee, C.P. Lo, ……, Meng-Fan Chang*, “A ReRAM-based Nonvolatile Flip-Flop with Self-Write-Termination Scheme for Frequent-Off Fast-Wakeup Nonvolatile Processors ,” IEEE Journal of Solid-State Circuits (JSSC), vol. 52, no. 8, pp. 2194-2207, Aug. 2017
33. Xueqing Li;   John Sampson;   Asif Khan;   Kaisheng Ma;   Sumitha George;   Ahmedullah Aziz;   Sumeet Kumar Gupta;   Sayeef Salahuddin;   Meng-Fan Chang;   Suman Datta;   Vijaykrishnan Narayanan, “Enabling Energy-Efficient Nonvolatile Computing With Negative Capacitance FET”, IEEE Transactions on Electron Devices, vol 64, no. 8, pp.3452-3458, Aug. 2017.
34. Xueqing Li;   Kaisheng Ma;   Sumitha George;   Win-San Khwa;   John Sampson;   Sumeet Gupta;   Yongpan Liu;   Meng-Fan Chang;   Suman Datta;   Vijaykrishnan Narayanan, “Design of Nonvolatile SRAM with Ferroelectric FETs for Energy-Efficient Backup and Restore,” IEEE Transactions on Electron Devices,  vol. 64, no. 7, pp. 3037-3040, July 2017.

35.  Keng-Hao Yang,   Hsiang-Jen Tsai,   Chia-Yin Li,   Paul Jendra,   Meng-Fan Chang, Tien-Fu Chen, “eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 4, pp. 858-868, April 2017

36. Hsiang-Jen Tsai,   Keng-Hao Yang,   Yin-Chi Peng,   Chien-Chen Lin,   Ya-Han Tsao,   Meng-Fan Chang,  Tien-Fu Chen, “Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol 25, no. 3, pp-962-973, March 2017.
37. M.-F. Chang*, et al, “A 3T1R Nonvolatile TCAM using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing,” IEEE Journal of Solid-State Circuits (JSSC), vol. 52, no. 6, pp. 1664-1679, June 2017
38. W-S. Khwa, M.-F. Chang,  et al., “A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100x for Storage Class Memory Applications,” IEEE Journal of Solid-State Circuits (JSSC), vol. 52, no. 1, pp. 218-228, Jan. 2017
39. M.-F. Chang*, L.-Y. Huang, et al, “A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing,” IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 11, pp. 2786-2798, Nov. 2016.
40. W-S. Khwa, M.-F. Chang, et al., “A Retention-Aware Multilevel Cell Phase Change Memory Program Evkhwaaluation Metric”, IEEE Electron Device Letters, no.37, pp. 1422-1425, Nov. 2016

41.  M.-F. Chang*, J.-J. Wu, T.-F. Chien, Y.-C. Liu, T.-C. Yang, W.-C. Shen, Y.-C. King, C.-J. Lin, K.-F. Lin, Y.-D. Chih, and J. Chang, “Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros against Resistance and Switch-Time Variations,” IEEE Journal of Solid-State Circuits (JSSC), vol. 50, no. 11, pp. 2786-2795, Nov. 2015.

42.  M.-F. Chang*, Y.-F. Lin, Y.-C. Liu, J.-J. Wu, S.-J. Shen, W.-C. Tsai, and Y.-D. Chih, “An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros,” IEEE Journal of Solid-State Circuits (JSSC), vol. 50, no. 9, pp. 2188-2198, Sept. 2015.

43. M.-F. Chang*, Albert Lee, P.-C. Chen, C. J. Lin, Y.-C. King, S.-S. Sheu, and T.-K. Ku, “"Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 5, no. 2, pp. 183-193, June 2015.
44. C.-H. Hung, M.-F. Chang*, Y.-S. Yang, Y.-J. Kuo, T.-N. Lai, S.-J. Shen, J.-Y. Hsu, S.-N. Hung, H.-T. Lue, Y.-H. Shih, S.-L. Huang, T.-W. Chen, T. -S. Chen, C. K. Chen, C.-Y. Hung, and C.-Y. Lu, “Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash against Cross-Layer Process Variations,” IEEE Journal of Solid-State Circuits (JSSC), vol. 50, no. 6, pp. 1491-1501, June 2015.

45.  M.-F. Chang*, S.-M. Yang, C.-C. Kuo, T.-C. Yang, C.-J. Yeh, T.-F. Chien, L.-Y. Huang, S.-S. Sheu, P.-L. Tseng and T.-K. Ku, “Set-Triggered-Parallel-Reset Memristor Logics for High-Density Heterogeneous-Integration Friendly Normally-Off Applications,” IEEE Transactions on Circuits and Systems II, vol. 62, no. 1, pp. 80-84, Jan. 2015.

46. W. Y. Hsiao, P. C. Peng,  T.-S. Chang, Y.-D. Chih, W.-C. Tsai,   M.-F. Chang, T.-F. Chien, Y.-C. King, and C.-J. Lin*, “A New High-Density Twin-Gate Isolation One-Time Programmable Memory Cell in Pure 28-nm CMOS Logic Process,” IEEE Transactions on Electron Devices, vol. 62, no. 1, pp. 121 – 127, Jan. 2015.
47. S.-W. Chiu, J.-H. Wang, K.-H. Chang, T.-H. Chang, C.-M. Wang, C.-L. Chang, C.-T. Tang, C.-F. Chen, C.-H. Shih, H.-W. Kuo, L.-C. Wang, H. Chen, C.-C. Hsieh, M.-F. Chang, Y.-W. Liu, T.-J. Chen,  C.-H. Yang, H. M. Chiueh, J.-M. Shyu, K.-T. Tang*, “A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia,” IEEE Transactions on Biomedical Circuits and Systems, vol. 8, no. 6, pp 765-778, June 2014.

48.  M.-F. Chang*, C.-C. Kuo, S.-S. Sheu, C.-J. Lin, Y.-C. King, F. T. Chen, T.-K. Ku, M.-J. Tsai, J.-J. Wu, and Y.-D. Chih, “Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme,” IEEE Journal of Solid-State Circuits (JSSC), vol. 49, no. 4, pp. 908-916, April 2014.

49.  M.-F. Chang*, M.-P. Chen, L.-F. Chen, S.-M. Yang, Y.-J. Kuo, J.-J. Wu, H.-Y. Su, Y.-H. Chu, W.-C. Wu, T.-Y. Yang, and H. Yamauchi, “A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-Vth Read-Port, and Offset Cell VDD Biasing Techniques,” IEEE Journal of Solid-State Circuits (JSSC), vol. 48, no. 10, pp. 2558-2569, Oct. 2013.

50.  M.-F. Chang*, C.-W. Wu, C.-C. Kuo, S.-J. Shen, S.-M. Yang, K.-F. Lin, W.-C. Shen, Y.-C. King, C.-J. Lin, and Y.-D. Chih, “A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5V 4Mb 65nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro,” IEEE Journal of Solid-State Circuits (JSSC), vol. 48, no. 9, pp. 2250-2259, Sept. 2013.

51.  M.-F. Chang*, et al., “A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms,” IEEE Journal of Solid-State Circuits (JSSC), vol. 48, no. 6, pp. 1521-1529, June 2013.

52.  W.-T. Chen, Y.-L. Lin, C.-Y. Lee, J.-L. Chiang, M.-F. Chang, and S.-C. Chang*, “Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan,” IEEE Access, vol. 1, pp. 123-130, June 2013.

53.  M.-F. Chang*, et al., “A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes,” IEEE Journal of Solid-State Circuits (JSSC), vol. 48, no. 3, pp. 878-891, March 2013.

54.  M.-F. Chang*, et al., “An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory,” IEEE Journal of Solid-State Circuits (JSSC), vol. 48, no. 3, pp. 864-877, March 2013.

55.  S.-M. Yang, M.-F. Chang*, et al., “Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for Speed and Power Improvement,” IEEE Journal of Solid-State Circuits (JSSC), vol. 48, no. 2, pp. 611-623, Feb. 2013.

56.  J.-J. Wu, M.-F. Chang*, S.-W. Lu, R. Lo, and Q. Li, “A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous Access Disturbances,” IEEE Transactions on Circuits and Systems II, vol. 59, no. 11, pp. 790-794, Nov. 2012.

57.  P.-F. Chiu, M. F. Chang*, C.-W. Wu, C.-H. Chuang, S.-S. Sheu, Y.-S. Chen, and M.-J. Tsai, “Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM with Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications,” IEEE Journal of Solid-State Circuits (JSSC), vol. 47, no. 6, pp. 1483-1496 , June 2012.

58.  Y.-H. Chen, S.-Y. Chou, Q. Li, W.-M. Chan, D. Sun, H.-J. Liao, P. Wang, M.-F. Chang*, and H. Yamauchi, “Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in A 40nm Fully Functional Embedded SRAM,” IEEE Journal of Solid-State Circuits (JSSC), vol. 47, no. 4, pp. 969-980, April 2012.

59.  C.-H. Wang, Y.-H. Tsai, K.-C. Lin, M.-F. Chang, Y.-C. King, C. J. Lin*, et al., “Three-Dimensional 4F2 ReRAM with Vertical BJT Driver by CMOS Logic Compatible Process," IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2466-2472, Aug. 2011.

60.  K.-T. Tang*,   S.-W. Chiu,   M.-F. Chang,   C.-C. Hsieh and   J.-M. Shyu, “A Low-Power Electronic Nose Signal-Processing Chip for a Portable Artificial Olfaction System,” IEEE Transactions on Biomedical Circuits and Systems, vol. 5, no. 4, pp. 380-390, Aug. 2011.

61.  J.-J. Wu, Y.-H. Chen, M.-F. Chang*, P.-W. Chou, C.-Y. Chen, H.-J. Liao, M.-B. Chen, Y.-H. Chu, W.-C. Wu, and H. Yamauchi, “A Large σVTH/VDD Tolerant Zigzag 8T SRAM with Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme," IEEE Journal of Solid-State Circuits (JSSC), vol. 46, no. 4, pp. 815-827, April 2011.

62.  M.-F. Chang*, S.-W. Chang, P.-W. Chou and W.-C. Wu, “A 130mV SRAM with Expanded Write and Read Margins for Subthreshold Applications," IEEE Journal of Solid-State Circuits (JSSC), vol. 46, no. 2, pp. 520-529, Feb. 2011.

63.  S.-S. Sheu*, K.-H. Cheng, M.-F. Chang, et al., “Fast Access Speed RRAM for Embedded Applications,” IEEE Design and Test of Computers, vol. 28. no. 1, pp. 64-71, Jan. 2011.

64.  M.-F. Chang*, Y.-C. Chen and C.-F. Chen, “A 0.45V 300MHz 10T Flow-Through SRAM with Expanded Write/Read Stability and Speed-Area-Wise Array for sub-0.5V Chips," IEEE Transactions on Circuits and Systems II, vol. 57, no. 12, pp. 980-985, Dec. 2010.

65.  M.-F. Chang*, S.-M. Yang, C.-W. Liang, C.-C. Chiang, P.-F. Chiu, and K.-F. Lin, “Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-line Scheme for VDDmin and Speed Improvements,” IEEE Journal of Solid-State Circuits (JSSC), vol. 45, no. 10, pp. 2142-2155, Oct. 2010.

66.  M.-F. Chang*, J.-J. Wu, K.-T. Chen, Y.-C. Chen, Y.-H. Chen, R. Lee, H.-J. Liao and H. Yamauchi, “A Differential Data Aware Power-supplied (D2AP) 8T SRAM Cell with Expanded Write/Read Stabilities for Lower VDDmin Applications,” IEEE Journal of Solid-State Circuits (JSSC), vol. 45, no. 6, pp. 1234-1245, June 2010.

67.  M.-F. Chang* and S.-J. Shen,“A process variation tolerant embedded split-gate Flash memory using pre-stable current sensing scheme,” IEEE Journal of Solid-State Circuits (JSSC), vol. 44, no. 3, pp.987-994, March 2009. (SCI)

68.  M.-F. Chang*, S.-M. Yang, and K.-T. Chen, “Wide-VDD embedded asynchronous SRAM with dual-mode self-timed technique for dynamic voltage systems,” IEEE Transactions on Circuits and Systems I, vol. 56, no. 8 pp. 1657-1667, Aug. 2009. (SCI)

69.  M.-F. Chang* and S.-M. Yang, “Analysis and reduction of supply noise fluctuations induced by embedded ROM,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 6, pp. 758-769, June 2009. (SCI)

70.  M.-F. Chang*, L.-Y. Chiou, and K.-A. Wen, “Crosstalk-insensitive via-programming ROMs using content-aware design framework,” IEEE Transactions on Circuits and Systems II, vol. 53, issue 6, pp. 443-447, June 2006. (SCI)

71.  M.-F. Chang*, L.-Y. Chiou, and K.-A. Wen, “A full code-pattern coverage high-speed embedded ROM using dynamic virtual guardian technique,” IEEE Journal of Solid-State Circuits (JSSC), vol. 41, no. 2, pp. 496-506, Feb. 2006. (SCI)

72.  M.-F. Chang*, L.-Y. Chiou, and K.-A. Wen, “Code-pattern insensitive embedded ROMs using dynamic bitline shielding technique,” IEE Electronics Letters, vol. 41, no. 15, pp. 834-835, July 2005. (SCI)

73.  M.-F. Chang* and K.-A. Wen, “Power and substrate noise tolerance of configurable embedded memories in SoC”, Journal of VLSI Signal Processing Systems, Special Issue on System-on-a-Chip, vol. 41, no. 1, pp.81-91, Aug. 2005. (EI)

74.  M.-F. Chang, M. J. Irwin*, and R. M. Owens, “Power-area tradeoff in dual word line memory cell arrays,” Journal of Circuits, Systems and Computers, vol. 7, no. 1, pp. 49–67, Feb. 1997. (EI)