Publications

Journal Papers

Conference Papers

Invited Conference Talks and Papers

Patents

Book Chapters and others

 

Highlights (updated on Jan 2021)

l   70+ top conference papers: ISSCC (31), VLSI Symp. (22), IEDM (14), DAC (6)

Conference Papers (研討會論文)

          (* Corresponding author)

1.     Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Tianlong Pan, Sih-Han Li, Shih-Chieh Chang , Shyh-Shyuan Sheu, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang*, "A 28nm 384Kb 6T SRAM Computation-in-memory Macro with 8b-precision for AI Edge Chips," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 250-251, Feb. 2021

2.     Cheng-Xin Xue, Je-Min Hung, Hui-Yao Kao, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Peng Chen, Ta-Wei Liu, Chuan-Jia Jhang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang*, "A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91-195.7 TOPS/W for Tiny AI Edge Devices," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 246-247, Feb. 2021

3.     Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yu-Lin Chen, Chieh-Pu Lo, Cheng-Han Lu, Haruki Mori, Wei-Chang Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan-Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yih Wang, Meng-Fan Chang, Tsung-Yung Jonathan Chang, “An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications,”IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 252-253, Feb. 2021

4.     Ruiqi Guo, Zhiheng Yue, Xin Si, Te Hu, Hao Li, Limei Tang, Yabing Wang, Leibo Liu, Meng-Fan Chang, Qiang Li, Shaojun Wei, Shouyi Yin*, " A 5.99-to-691.1 TOPS/W Tensor-train In-Memory-Computing Processor using Bit-Level Sparsity based Optimization and Variable-Precision Quantization," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 242-243, Feb. 2021.

5.     Zhe Yuan, Mingtao Zhan, Jiaxin Liu, Jian-Wei Su, Yen-Lin Chung, Ping-Chun Wu, Li-Yang Hung, Meng-Fan Chang, Nan Sun, Xueqing Li, Huazhong Yang, Yongpan Liu*, " A 2.75-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 238-239, Feb. 2021.

6.     Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury*, “A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute- in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification, IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 404-405, Feb. 2021.

7.     Fu-Kuo Hsueh1 , Je-Min Hung2 , Sheng-Po Huang2 , Yen-Hsiang Huang2 , Cheng-Xin Xue , Chang-Hong Shen*, Jia-Min Shieh*, Wen-Cheng Chiu1 , Chao-Cheng Lin1 , Bo-Yuan Chen1 , Szu-Ching Liu1 , Shih-Wei Chen1 , Deng-Yan Niou1 , Wen-Hsien Huang1 , Kai-Shin Li1 , Kun-Kin Lin1 , Da-Chiang Chang1 , Kun-Ming Chen1 , Guo-Wei Huang1 , Ci-Ling Pan2 , Meng-Fan Chang*, Chenming Hu, and Wen-Kuan Yeh, “First Demonstration of Ultrafast Laser Annealed Monolithic 3D Gate-All-Around CMOS Logic and FeFET Memory with Near-Memory-Computing Macro,” IEEE International Electron Devices Meeting (IEDM) , pp.28.5.1-28.5.4, Dec. 2020

8.     Akshay Krishna Ramanathan1 , Srivatsa Srinivasa Rangachar2 , Je-Min Hung3 , Chun-Ying Lee3 , Cheng-Xin Xue3 , ShengPo Huang3 , Fu-Kuo Hsueh4 , Chang-Hong Shen4 , Jia-Min Shieh4 , Wen-Kuan Yeh4 , Mon-Shu Ho5 , Hariram Thirucherai Govindarajan1 , Jack Sampson1 , Meng-Fan Chang* , Vijaykrishnan Narayanan,” Monolithic 3D+-IC Based Massively Parallel Compute-in-Memory Macro for Accelerating Database and Machine Learning Primitives” IEEE International Electron Devices Meeting (IEDM) , pp.40.4.1-40.4.4, Dec. 2020

9.     Jianguo Yang, Xiaoyong Xue, Xiaoxin Xu, Hangbing Lv, Feng Zhang, Xiaoyang Zeng, Meng-Fan Chang, Ming Liu, “A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm2 using Sneaking Current Suppression and Compensation Techniques”, Symposium on VLSI Circuits (VLSI Symp.), June 2020

10.  Hongwu Jiang;Shanshi Huang;Xiaochen Peng;Jian-Wei Su;Yen-Chi Chou;Wei-Hsing Huang;Ta-Wei Liu;Ruhui Liu;Meng-Fan Chang;Shimeng Yu, “A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training,” in Proc. Design Automation Conference (DAC), pp. 1-6, June 2020

11.  C.-X. Xue..., M.-F. Chang* “A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices.” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 244-245, Feb. 2020

12.  J.-W. Su..., M.-F. Chang* “A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 240-241, Feb. 2020

13.  X. Si..., M.-F. Chang* “A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 246-247, Feb. 2020

14.  T.-C. Chang..., M.-F. Chang* “A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices.” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 224-225, Feb. 2020

15.  Jinshan Yue, Zhe Yuan, Xiaoyu Feng, Yifan He, Zhixiao Zhang, Xin Si, Ruhui Liu,   Meng-Fan Chang, Xueqing Li, Huazhong Yang, Yongpan Liu*, “A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse,”  IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 234-235, Feb. 2020

16.  Tzu-Hsiang Hsu, Yen-Kai Chen, Jun-Shen Wu, Wen-Chien Ting, Cheng-Te Wang,   Chen-Fu Yeh, Syuan-Hao Sie, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh*, “A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel, “ IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 110-111, Feb. 2020

17.  Qi Liu, Bin Gao, Peng Yao, Dong Wu, Junren Chen, Yachuan Pang, Wenqiang Zhang, Yan Liao, Cheng-Xin Xue, Wei-Hao Chen, Jianshi Tang, Yu Wang, Meng-Fan Chang, He Qian, Huaqiang Wu*, “A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 500-501, Feb. 2020

18.  T.-H. Hsu..., M.-F. Chang and C.-C. Hsieh*, “AI Edge Devices Using Computing-In-Memory and Processing-In-Sensor: From System to Device.” IEEE International Electron Devices Meeting (IEDM) , pp.530-533, Dec. 2019

19.  F.-K. Hsueh..., M.-F. Chang ..., and W.-K. Yeh*, “Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETs.” IEEE International Electron Devices Meeting (IEDM), pp.54-57, Dec. 2019

20.   Z. Zhang..., M.-F. Chang*, “A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors.” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.217-218, Nov. 2019

21.  T.-H. Hsu..., M.-F. Chang and C.-C. Hsieh*, “A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction.” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.33-36, Dec. 2019

22.  C.-X. Xue, M.-F. Chang* “Challenges in Circuit Designs of Nonvolatile-memory based computing-in-memory for AI Edge Devices.” International SoC Design Conference (ISOCC) , pp.164-165, Oct. 2019

23.  X. Si..., M.-F. Chang* “Circuit Design Challenges in Computing-in-Memory for AI Edge Devices.” IEEE 13th International Conference on ASIC (ASICON) , Oct. 2019

24.  K.-T. Tang..., M.-F. Chang, “Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices.” IEEE Symposium on VLSI Circuits (VLSI Symp.), C166-C167, June, 2019

25.  Y.-C. Chiu..., M.-F. Chang* , “A 40nm 2Mb ReRAM Macro with 85% Reduction in FORMING Time and 99% Reduction in Page-Write Time Using Auto-FORMING and Auto-Write Schemes.” IEEE Symposium on VLSI Technology (VLSI Symp.), T232-T233, June, 2019

26.  B. Yan..., M.-F. Chang , and H Li*, “RRAM-based Spiking Nonvolatile Computing-In-Memory Processing Engine with Precision-Configurable In Situ Nonlinear Activation.” IEEE Symposium on VLSI Technology (VLSI Symp.) , T86-T87, June, 2019

27.   S. Srinivasa..., M.-F. Chang* ,and V. Narayanan*, “Monolithic 3D+-IC Based Reconfigurable Compute-in-Memory SRAM Macro.” IEEE Symposium on VLSI Technology (VLSI Symp.), T32-T33, June, 2019

28.  R. Guo, …, M.-F. Chang, S. Wei, and S. Yin, “A 5.1pJ/Neuron 127.3us/Inference RNN-Based Speech Recognition Processor Using 16 Computing-in-Memory SRAM Macros in 65nm CMOS”, Symposium on VLSI Ciruits (VLSI Symp.), pp. C120-C121, June 2019  (THU accepted)

29.  C.-X. Xue, M.-F. Chang*, “A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing time for CNN-based AI Edge Processors,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 388-390, Feb. 2019

30.  X. Si, ., M.-F. Chang*, “A Twin-8T SRAM Computation-In-Memory Macro for Multiple-bits CNN-Based Machine Learning,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 396-398, Feb. 2019

31.  J. Yue, …M.-F. Chang, X. Li, H. Yang, Y. Liu*, “A 65nm 0.39-140.3 TOPS/W 1-12bit Unified Neural Network Processor Using Block-circulant Enabled Transpose-Domain Acceleration with 8.1x Higher TOPS/mm2 and 6T HBST-TRAM Based 2D Data Reuse Architecture,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 138-140, Feb. 2019

32.  Y. Pang, …., M.-F. Chang, H. Wu*, ”A Reconfigurable RRAM Physical Unclonable Function Utilizing Post-Process Randomness Source with < 6E-6 Nature Bit Error Rate,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 402-404, Feb. 2019

33.  Fu-Kuo Hsueh, …. Vijaykrishnan Narayanan, Meng-Fan Chang*, and Wen-Kuan Yeh, “Ultra-Low Power 3D NC-FinFET-based Monolithic 3D+-IC with Computing-in-Memory for Intelligent IoT Devices, “IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 15.1.1-15.1.4, Dec. 2018

34.  Kai-Shin Li     ;    Fu-Kuo Hsueh     ;    Chang-Hong Shen     ;    Jia-Min Shieh     ;    Hsiu-Chih Chen     ;    Wen-Hsien Huang     ;    Hsiao-Yun Chiu     ;    Chih-Chao Yang     ;    Tung-Ying Hsieh     ;    Bo-Yuan Chen     ;    Wei-Hao Chen     ;    Kuo-Hsiang Hsu     ;    Meng-Fan Chang     ;    Wen-Kuan Yeh , “FinFET-based Monolithic 3D+ with RRAM Array and Computing in Memory SRAM for Intelligent IoT Chip Application,” 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 1-3, 2018

35.  Meng-Yao Lin,  Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang, “DL-RSIM: A Simulation Framework to Enable Reliable ReRAM-based Accelerators for Deep Learning ,” ICCAD, pp. 1-8, 2018

36.  Pin-Yi Li, Cheng-Han Yang, Wei-Hao Chen, Jian-Hao Huang, Wei-Chen Wei, Je-Syu Liu, Wei-Yu Lin, Zu- Hsiang Hs,  Chih-Cheng Hsieh, Ren-Shuo Liu, Meng-Fan Chang, Kea-Tiong Tang*, “A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array,” IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. xx-xx, 2018.  

37.  Cheng-Xin Xue, Wei-Cheng Zhao, Tzu-Hsien Yang, Yi-Ju Chen, Hiroyuki Yamauchi and Meng-Fan Chang, “A 28nm 320Kb TCAM Macro with Sub-0.8ns Search Time and 3.5+x Improvement in Delay-Area-Energy Product using Split-Controlled Single-Load 14T Cell”, IEEE Asia Solid-State Circuits Conference (A-SSCC), pp. 127-128, Nov. 2018.

38.  C. Dou, W.-H. Chen, C.-X. Xue, W.-Y. Lin, W.-E. Lin, J.-Y. Li, H.-T. Lin, and M.-F. Chang*, “Nonvolatile Circuits-Devices Interaction for Memory, Logic and Artificial Intelligence” Symposium on VLSI Technology (VLSI Symp.), pp. 171-172, June 2018 (invited)

39.  Z. Yuan, J. Yue, H. Yang, Z. Wang, J. Li, Y. Yang, Q. Guo, X. Li, M.-F. Chang,     H. Yang, Y. Liu*, “Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers” Symposium on VLSI Circuits (VLSI Symp.), pp. 33-34, June 2018

40.  R. Liu, …M.-F. Chang and S. Yu, “Parallelizing SRAM Arrays with Customized Bit-Cell for Binary Neural Networks,” in Proc. Design Automation Conference (DAC), pp. 1-6, June 2018

41.  Yixiong Yang,  Zhibo Wang, Pei Yang,  Meng-Fan Chang, Mon-Shu Ho, Huazhong Yang, Yongpan Liu , “A 2-GHz Direct Digital Frequency Synthesizer Based on LUT and Rotation,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, 2018   

42.  W.-H. Chen, …., M.-F. Chang*, “A 65nm 1Mb Nonvolatile Computing-in-Memory ReRAM Macro with sub-16ns Multiply-and-Accumulate for Binary DNN AI Edge Processors,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 494-495, Feb. 2018

43.  V. Khwa, …., M.-F. Chang*, “A 65nm 4Kb Algorithm-Dependent Computing-in-Memory SRAM Unit-Macro with 2.3ns and 55.8 TOPS/W Fully Parallel Product-Sum Operation for Binary DNN Edge Processors,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 496-497, Feb. 2018

44.  T.-H. Yang, …., M.-F. Chang*, “A 28nm 32Kb Embedded 2T2MTJ STT-MRAM Macro with 1.3ns Read-Access-Time for Fast and Reliable Read Applications,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 480-481, Feb. 2018

45.  W.-H. Chen, …M.-F. Chang*, “A 16Mb Dual-Mode ReRAM Macro with Sub-14ns Computing-In-Memory and Memory Functions Enabled by Self-Write Termination Scheme,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 28.2.1-28.2.4, Dec. 2017

46.  F.-K. Hsueh, …, M.F. Chang, and W.-K. Yeh, “TSV-free FinFET-based Monolithic 3D+-IC with Computing-in-Memory SRAM Cell for Intelligent IoT Devices” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 12.6.1-12.6.4, Dec. 2017

  1. Feng Zhang;   Dongyu Fan;   Yuan Duan;   Jin Li;   Cong Fang;   Yun Li;   Xiaowei Han;   Lan Dai;   Chengying Chen;   Jinshun Bi;   Ming Liu;   Meng-Fan Chang  , “A 130nm 1Mb HfOx embedded RRAM macro using self-adaptive peripheral circuit system techniques for 1.6X work temperature range ,” 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 173-176, Nov. 2017
  2. M.-F. Chang, “Challenges of emerging memory and memristor based circuits: Nonvolatile logics, IoT security, deep learning and neuromorphic computing,“ IEEE 12th International Conference on ASIC (ASICON) , pp. 140-143, Oct. 2017 (Invited Talk/Paper)

49.  Srivatsa Rangachar Srinivasa;   Karthik Mohan;   Wei-Hao Chen;   Kuo-Hsinag Hsu;   Xueqing Li;   Meng-Fan Chang;   Sumeet Kumar Gupta;   John Sampson;   Vijaykrishnan Narayanan, “Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via,”  2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp128-133, 2017

50.  C.-P. Lo, …M.F. Chang*, “Embedded 2Mb ReRAM Macro with 2.6ns Read Access Time Using Dynamic- Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier for IoE Applications”, Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. C164-C165, June 2017.

51.  F. Su, …M.-F. Chang, H. Yang, Y. Liu, “A 462GOPs/J RRAM-Based Nonvolatile Intelligent Processor for Energy Harvesting IoE System Featuring Nonvolatile Logics and Processing-In-Memory” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. T260-T261, June 2017.

52.  F. Su,…M.-F. Chang, H. Yang, Y. Liu, “A 130nm FeRAM-Based Energy Harvesting Nonvolatile System-On-Chip with 5.2x Higher Performance & 26.9x Faster System Wakeup Using Adaptive Load Balance and Fast Peripheral Startup Schemes,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. C260-C261, June 2017.

  1. W. H. Chen, .., M.-F. Chang*, “Circuit Design for Beyond Von Neumann Applications Using Emerging Memory: From Nonvolatile Logics to Neuromorphic Computing,” in Proc. International Symposium on Quality Electronic Design (ISQED), pp. 23-28 March 2017. (Invited Paper/special session)

54.  C.-P. Lo, W.-H. Chen, …., M.-F. Chang*, ” A ReRAM-based Single-NVM Nonvolatile Flip-Flop with Reduced Stress-Time and Write-Power against Wide Distribution in Write-Time by Using Self-Write-Termination Scheme for Nonvolatile Processors in IoT Era,“ IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 16.3.1-16.3.4, Dec. 2016.

  1. Ra-Min Tain;   Dyi-Chung Hu;   Kai-Ming Yang;   Yu-Hua Chen;   Chih-Lun Wang;   Cheng-Hsiung Wang;   Ching Chang;   Yan-bin Chang;   Zih-Yu Ciou;   Han-Wen Hu;   Meng-Fan Chang, “SiP assembly and application using glass substrate with through vias ”  2016 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), pp. 281-284, 2016
  2. Fang Su;   Zhibo Wang;   Jinyang Li;   Meng-Fan Chang;   Yongpan Liu , “ Design of nonvolatile processors and applications,” 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp.1-6, 2016
  3. M.-F. Chang, et al., “A sub-0.5V charge pump circuit for resistive RAM (ReRAM) enabled low supply voltage nonvolatile logics and nonvoaltile processors,” in Proc. IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 342-345, Aug. 2016 (invited)
  4. S. George, …, M.-F. Chang, …V. Narayanan, “Nonvolatile Memory Design Based on Ferroelectric FETs,” in Proc. Design Automation Conference (DAC), pp. 1-6, June 2016
  5. M.-F. Chang, et al, “Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1142-1145, May 2016. (invited)
  6. M.-H. Kao,   C,-C, Yang,   …,   M.-F. Chang;   J.-M. Shieh, “ a-SiGeC thin film photovoltaic enabled self-power monolithic 3D IC under indoor illumination”, in Proc. IEEE International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), pp. 1-2, April 2016

61.  C.-C. Lin, …., M.-F. Chang*, “A 256b-Wordlength ReRAM-based TCAM with 1ns Search-Time and 14x Improvement in WordLength-EnergyEfficiency-Density Product using 2.5T1R cell,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 136-137, Feb. 2016

62.  V. Khwa*, M.-F. Chang, …, “A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100X for Storage Class Memory Applications,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 134-135, Feb. 2016

63.  Y. Liu*,  …, M.-F. Chang, and H. Yang, “A 65nm ReRAM-Enabled Nonvolatile Processor with 6X Reduction in Restore Time and 4X Higher Clock Frequency Using Adaptive Data Retention and Self-Write-Termination Nonvolatile Logic,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 84-85, Feb. 2016

64.  T.T. Wu, C.-H. Shen*, J.-M. Shieh*,…., M.-F. Chang, and W.-K. Yeh, ” Low-Cost and TSV-free Monolithic 3D-IC with Heterogeneous Integration of Logic, Memory and Sensor Analogy Circuitry for Internet of Things,“ IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 25.4.1 - 25.4.4, Dec. 2015.

65.  A. Lee, M.-F. Chang*, et al., “ReRAM-based 7T1R Nonvolatile SRAM with 2x Reduction in Store Energy and 94x Reduction in Restore Energy for Frequent-Off Instant-On Applications,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 76-77, June 2015.

66.  M.-F. Chang*, et al., “Supply-Variation-Resilient Nonvolatile 3D IC and 3D Memory Using Low Peak-Current On-Chip Charge-Pump Circuits,” in Proc. IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 118-121, June 2015. (Invited Talk/Paper)

67.  H.-J. Tsai, …, M.-F. Chang and T.-F. Chen*, “Energy-Efficient Non-Volatile TCAM Search Engine Design Using Priority-Decision in Memory Technology for DPI,” in Proc. Design Automation Conference (DAC), pp. 1-6, June 2015

68.  Y. P. Liu*, …. M.-F. Chang, …, et al., “Ambient Energy Harvesting Nonvolatile Processors: From Circuit to System,” in Proc. Design Automation Conference (DAC), pp. 1-6, June 2015

69.  A. Lee, C.-C. Lin, T.-C. Yang, and M.-F. Chang*, “An embedded ReRAM Using a Small-offset Sense Amplifier for Low-Voltage Operations”, in Proc. IEEE International Symposium on VLSI Design, Automation and Testing (VLSI-DAT), pp. 1-4, April 2015

  1. H. Li ;   Y. Liu* ;   Q. Zhao,  Y. Gu,   X. Sheng,   G. Sun,   C. Zhang,  M.-F. Chang,   R. Luo,   and H. Z. Yang, “An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodes,” in Proc. Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 7-12, March 2015.

71.  M.-F. Chang*, C.-F. Chen, et al., “A 28nm 256Kb 6T-SRAM with 280mV Improvement in VMIN Using a Dual-Split-Control Assist Scheme” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 314-315, Feb. 2015.

72.  M.-F. Chang*, C.-C. Lin, et al., “A 3T1R Nonvolatile TCAM Using MLC ReRAM with Sub-1ns Search Time,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 318-319, Feb. 2015.

73.  M.-F. Chang*, et al., “Challenges at Sensing Circuits for Resistive Memory and Memristor-based Nonvolatile Logics,” in Proc. 2014 IEEE Asia South Pacific Design Automation Conference (ASP-DAC), pp. 569 – 574, Jan. 2015. (Invited Talk/Paper) (Tokyo, Japan)

74.  C.-H. Shen, J.-M. Shieh, W.-H. Huang, T.-T. Wu, C.-F. Chen, M.-H. Kao, C.-C. Yang, C.-D. Lin, H.-H. Wang, T.-Y. Hsieh, B.-Y. Chen, G.-W. Huang, M.-F. Chang, and F.-L. Yang, “Heterogeneously integrated sub-40nm low-power epi-like Ge/Si monolithic 3D-IC with stacked SiGeC ambient light harvester,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 3.6.1 - 3.6.4, Dec. 2014.

75.  W. S. Khwa, J.Y. Wu, T.H. Su, H. P. Li, M. BrightSky, T. Y. Wang, T. H. Hsu, P. Y. Du, R. Cheek, E. K. Lai, Y. Zhu, M.H. Lee, M. F. Chang, H.L. Lung, and C. Lam, “Novel Inspection and Annealing Procedure to Rejuvenate Phase Change Memory from Cycling-Induced Degradations for Storage Class Memory Applications,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 29.8.1 - 29.8.4, Dec. 2014.

76.  M.-F. Chang*, C.-W. Wu, J.-Y. Hung, Y.-C. King, and C.-J. Lin, M.-S. Ho, C.-C. Kuo and S.-S. Sheu, “A Low-Power Subthreshold-to-Superthreshold Level-Shifter for Sub-0.5V Embedded Resistive RAM (ReRAM) Macro in Ultra Low-Voltage Chips,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 695-698, Oct. 2014. (Best Paper Award)

  1. W.-P. Lin, S.-S. Sheu,   C.-C. Kuo,  P.-L. Tseng,  M.-F. Chang, K.-L. Su,  C.-S. Lin,  K.-H. Tsai, S.-H. Lee, S.-C. Liu, Y.-S. Chen, H.-Y. Lee,  C.-C. Hsu,   F.T. Chen,  T.-K. Ku, M.-J. Tsai, and M.-J. Kao, “A nonvolatile look-up table using ReRAM for reconfigurable logic,” in Proc. IEEE Asia Solid-State Circuits Conference (A-SSCC), pp. 133-136, Nov. 2014.

78.  M.-F. Chang*, Albert Lee, C.-C. Kuo, S.-Shyuan Sheu, Fredrick. T Chen, Tzu-Kun Ku, Yong-Pan Liu, Hua-Zhong Yang, Ping-Cheng Chen, “Challenges at Circuit Designs for Resistive-Type Nonvolatile Memory and Nonvolatile Logics in Mobile and Cloud Applications“, in Proc. IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1-4, Oct. 2014. (Invited Talk/Paper)

79.  L.-Y. Huang, M.-F. Chang*, C.-H. Chuang, C.-C. Kuo, C.-F. Chen, G.-H. Yang,  H.-J. Tsai, T.-F. Chen, S.-S. Sheu, K.-L. Su, F.T. Chen, T.-K. Ku, M.-J. Tsai, M.-J. Kao, “ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing “, Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 122-123, June 2014. (Hawaii, US)

80.  Hsiang-Jen Tsai, Chien-Chih Chen, Keng-Hao Yang, Ting-Chin Yang, Li-Yue Huang, Ching-Hao Chung, Meng-Fan Chang and Tien-Fu Chen*, “Leveraging Data Lifetime for Energy-aware Last Level Non-Volatile SRAM Caches using Redundant Store Elimination,” in Proc. IEEE Design Automation Conference (DAC), pp. 1-6, June 2014.

81.  M.-F. Chang*, J.-J. Wu, T.-F. Chien, Y.-C. Liu, T.-C. Yang, W.-C. Shen, Y.-C. King, C.-J. Lin, K.-F. Lin, Y.-D. Chih, S. Natarajan, and J. Chang, “Embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V Read Using Swing-Sample-and-Couple Sense Amplifier and Self-Boost-Write-Termination Scheme,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 332-333, Feb. 2014.

82.  K. T. Tang*, S-W. Chiu, C-H. Shih, C-L. Chang, C-M. Yang, D-J. Yao, J-H. Wang, C-M. Huang, H. Chen, K-H. Chang, C-C. Hsieh, T-H. Chang, M-F. Chang, C-M. Wang, Y-W. Liu, T-J. Chen, C-H. Yang, H. Chiueh, J-M. Shyu, et al., “A 0.5V 1.27mW Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 420-421, Feb. 2014.

83.  C.-H. Shen*, J.-M. Shieh, W.-H. Huang, T.-T. Wu, B.-Y. Chen, G.-W. Huang, Y.-C. Lien, C.-F. Chen, M.-F. Chang, C. Hu, and F.-L. Yang, “Monolithic 3D Chip Integrated with 500ns NVM, 3ps Logic Circuits and SRAM,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 232 – 235, Dec. 2013.

84.  Yen-Cheng Liu, Meng-Fan Chang*, Yu-Fan Lin, Jui-Jen Wu, Che-Ju Yeh, Shin-Jang Shen, Ping-Cheng Chen, Wu-Chin Tsai, Yu-Der Chih, Sreedhar Natarajan, “An Embedded Flash Macro with Sub-4ns Random-Read-Access Using Asymmetric-Voltage- Biased Current-Mode Sensing Scheme,” in Proc. IEEE Asia Solid-State Circuits Conference (A-SSCC), pp. 241-244, Nov. 2013. (Singapore)

85.  S.-S. Sheu*, C.-C. Kuo, M.-F. Chang, P.-L. Tseng, et al., “A ReRAM Integrated 7T2R Non-volatile SRAM for Normally-off Computing Application,” in Proc. IEEE Asia Solid-State Circuits Conference (A-SSCC), pp. 245-248, Nov. 2013. (Singapore)

86.  M.-F. Chang*, et al., “Area-Efficient Embedded RRAM Macros with Sub-5ns Random-Read-Access-Time Using Logic-Process Parasitic-BJT-Switch (0T1R) Cell and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 112-113, June 2013. (Kyoto, Japan)

87.  C.-H. Hung*, Y.-S. Yang, Y.-J. Kuo, T.-N. Lai, S.-J. Shen, J.-Y. Hsu, S.-N. Hung, H.-T. Lue, M.-F. Chang*, Y.-H. Shih, S.-L. Huang, T.-W. Chen, T. S. Chen, C. K. Chen, C.-Y. Hung, and C.-Y. Lu, “3D Stackable Vertical-Gate BE-SONOS NAND Flash with Layer-Aware Program-and-Read Schemes and Wave-Propagation Fail-Bit-Detection against Cross-Layer Process Variations,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 20-21, June 2013. (Kyoto, Japan)

88.  C. F. Chen, T.-H. Chang, L.-F. Chen, M.-F. Chang*, and H. Yamauchi, “A 210mV 7.3MHz 8T SRAM with Dual Data-Aware Write-Assists and Negative Read Wordline for High Cell-Stability, Speed and Area-Efficiency,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 130-131, June 2013. (Kyoto, Japan)

89.  M. B. Chen, L.F. Chen, M.-F. Chang*, S.-M. Yang, Y.-J. Kuo, J.-J. Wu, M.-S. Ho, H.-Y. Su, Y.-H. Chu, W.-C. Wu, T.-Y. Yang, and H. Yamauchi, “A 260mV L-shaped 7T SRAM with Bit-Line (BL) Swing Expansion Schemes Based on Boosted BL, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 112-113, June 2012. (Hawaii, US)

90.  M.-F. Chang*, C.-W. Wu, C.-C. Kuo, S.-J. Shen, S.-M. Yang, K.-F. Lin, Y.-C. King, C.-J. Lin, and Y.-D. Chih, “A 0.5V 4Mb Logic-Process Compatible Embedded Resistive RAM (ReRAM) in 65nm CMOS Using Low Voltage Current-Mode Sensing Scheme with 45ns Random Read Time," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 434-435, Feb. 2012.

91.  K.-T. Tang*, S.-W. Chiu, M.-F. Chang, C.-C. Hsieh, and J. M. Shyu, “A wearable Electronic Nose SoC for healthier living,” 2011 IEEE Biomedical Circuits and Systems Conference (BioCAS), pp.293-296, Nov. 2011.

  1. M.-F. Chang*, et al., “Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM),” in Proc. IEEE International Conference on ASIC (ASICON), pp. 299-302, Oct. 2011

93.  M.-F. Chang*, W.-C. Wu, C.-S. Lin, P.-F. Chiu, M.-B. Chen, Y.-H. Chen, H.-C. Lai, Z.-H. Lin, S.-S. Sheu, T.-K. Ku, and H. Yamauchi, “A Larger Stacked Layer Number Scalable TSV-based 3D-SRAM for High-Performance Universal-Memory-Capacity 3D-IC Platforms,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 74-75, June 2011. (Kyoto, Japan)

94.  Y.-H. Chen*, S.-Y. Chou, Q. Lee, W.-M. Chan, D. Sun, H.-J. Liao, P. Wang, M.-F. Chang, and H. Yamauchi, “A 40nm Fully Functional SRAM with BL Swing and WL Pulse Measurement Scheme for Eliminating a Need for Additional Sensing Tolerance Margins,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 70-71, June 2011. (Kyoto, Japan)

95.  M.-F. Chang*, S.-J. Shen, C.-C. Liu, C.-W. Wu, Y.-F. Lin, S.-C. Wu, C.-E. Huang, H.-C. Lai, Y.-C. King, C.-J. Lin, H.-J. Liao, Y.-D. Chih, H. Yamauchi, “An offset tolerant current-sampling-based sense amplifier for sub-100nA-cell-current nonvolatile memory," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 206-207, Feb 2011.

96.  S.-S. Sheu, M.-F. Chang*, K.-F. Lin, C.-W. Wu, Y.-S. Chen, P.-F. Chiu, C.-C. Kuo, Y.-S. Yang, P.-C. Chiang, W.-P. Lin, C.-H. Lin, H.-Y. Lee, P.-Y. Gu, S.-M. Wang, F. T. Chen, K.-L. Su, C.-H. Lien, K.-H. Cheng, H.-T. Wu, T.-K. Ku, M.-J. Kao, and M.-J. Tsai, “A 4Mb embedded SLC Resistive-RAM macro with 7.2ns read-write random access time and 160ns MLC-access capability," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 200-201, Feb 2011.

97.  C.-H. Wang, Y.-H. Tsai, K.-C. Lin, M.-F. Chang, Y.-C. King, C. J. Lin*, S.-S. Sheu, Y.-S. Chen, H.-Y. Lee, F. T. Chen, and M.-J. Tsai, “3-Dimensional 4F2 ReRAM Cell with CMOS Logic Compatible Process,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp.: 29.6.1 - 29.6.4, Dec. 2010.

98.  P.-F. Chiu, M.-F. Chang*, S.-S. Sheu, K.-F. Lin, P.-C. Chiang, C.-W. Wu, W.-P. Lin, C.-H. Lin, C.-C. Hsu, F.T. Chen, K.-L. Su, M.-J. Kao, M.-J. Tsai, “A Low Store Energy, Low VDDmin, Nonvolatile 8T2R SRAM with 3D Stacked RRAM Devices for Low Power Mobile Applications,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 229-230, June 2010. (Hawaii, US)

99.  J.-J. Wu, Y.-H. Chen, M.-F. Chang*, P.-W. Chou, Ch.-Y. Chen, H.-J., Liao, M.-B. Chen, Y.-H. Chu, W.-C. Wu, and H. Yamauchi, “A Large σVTH/VDD Tolerant Zigzag 8T SRAM with Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 103-104, June 2010. (Hawaii, US)

100.     M.-F. Chang*, S.-M. Yang, C.-W. Liang, C.-C. Chiang, P.-F. Chiu, K.-F. Lin, Y.-H. Chu, W.-C. Wu, and H. Yamauchi, “A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 266-267, Feb 2010. (San Francisco, US)

101.     M.-F. Chang*, J.-J. Wu, K.-T. Chen, and H. Yamauchi, “A differential data aware power-supplied (D2AP) 8T SRAM cell with expanded write/read stabilities for lower VDDmin applications," Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 156-157, June 2009. (Kyoto, Japan)

102.     M.-F. Chang*, S.-M. Yang, K.-T. Chen, H.-J. Liao and R. Lee, “Improving the speed and power of compilable SRAM using dual-mode self-timed technique," in Proc. IEEE International Workshop on Memory Technology, Design, and Testing (MTDT), pp. 57-60, Dec. 2007.

103.     M.-F. Chang*, D.-M. Kwai, S.-M. Yang, Y.-F. Chou, and P.-C. Chen, “Experiments on reducing standby current for compilable SRAM using hidden clustered source line control," in Proc. IEEE International Conference on ASIC (ASICON), pp. 1038-1041, Oct. 2007.

104.     D.-M. Kwai*, Y.-F. Chou, M.-F. Chang, et al.,“FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment,” in Proc. IEEE International Workshop on Memory Technology, Design, and Testing (MTDT), pp. 28-33, Aug. 2006.

105.     M.-F. Chang*, D.-M. Kwai, and K.-A. Wen, “Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding technique,” in Proc. IEEE International Workshop on Memory Technology, Design, and Testing (MTDT), pp. 16-21, Aug. 2005.

106.     M.-F. Chang*, L.-Y. Chiou, and K.-A. Wen, “A low supply noise content sensitive ROM architecture for SoC,” in Proc. IEEE Asia-Pacific Conference on Circuits and Systems, pp. 1021-1024, Dec. 2004.

107.     M.-F. Chang*, K.-A. Wen and D.-M. Kwai, “Supply and substrate noise tolerance using dynamic tracking clusters in configurable memory designs,” in Proc. IEEE Int’l  Symp. Quality Electronic Design (ISQED), pp. 297-302, Mar. 2004. (Oral)