•  Yu-Hsien Kao, Chang-Ming Lai, Jen-Ming Wu, Po-Chiun Huang, Ping-Hsuan Hsieh, Ta-Shun Chu, “A frequency-defined vernier digital-to-time converter for impulse radar systems in 65nm CMOS,” in IEEE International Solid-State Circuits Conference, February 2014.

•  Ping-Hsuan Hsieh and Tao Chiang, “An RF energy harvester with 35.7% PCE at PIN of –15 dBm,” in IEEE Symposium on VLSI Circuits, June 2013.

•  Yong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert Montoye, Leland Chang, Jose Tierno, and Daniel Friedman, “A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI,” in IEEE International Solid-State Circuits Conference, February 2013.

•  J. Bulzacchelli, T. Beukema, D. Storaska, P.-H. Hsieh, S. Rylov, D. Furrer, D. Gardellini, A. Prati, C. Menolfi, D. Hanson, J. Hertle, T. Morf, V. Sharma, R. Kelkar, H. Ainspan, W. Kelly, G. Ritter, J. Garlett, R. Callan, T. Toifl, and D. Friedman, “A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology,” in IEEE International Solid-State Circuits Conference, February 2012.

•  Ping-Hsuan Hsieh, Jay Maxey, and Chih-Kong Ken Yang, “A non-linear phase detector for digital phase locked loops,” in IEEE Custom Integrated Circuits Conference, September 2009.

•  Ping-Hsuan Hsieh, Jay Maxey, and Chih-Kong Ken Yang, “A bandwidth tracking technique for a 65nm CMOS digital phase-locked loop,” in IEEE Symposium on VLSI Circuits, June 2009.

•  Ping-Hsuan Hsieh, Jay Maxey, and Chih-Kong Ken Yang, “Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltage,” in IEEE Custom Integrated Circuits Conference, September 2008.

•  Ping-Hsuan Hsieh, Jack Judy, and Chih-Kong Ken Yang, “Varactor-less CMOS LC Oscillator using Variable Mean Frequency,” in IEEE Custom Integrated Circuits Conference, September 2003.

•  J. F. Bulzacchelli, C. Menolfi, T. J. Beukema, D. W. Storaska, J. Hertle, D. R. Hanson, P.-H. Hsieh, S. V. Rylov, D. Furrer, D. Gardellini, A. Prati, T. Morf, V. Sharma, R. Kelkar, H. A. Ainspan, W. R. Kelly, L. R. Chieco, G. A. Ritter, J. A. Sorice, J. D. Garlett, R. Callan, M. Brändli, P. Buchmann, M. Kossel, T. Toifl, and D. J. Friedman, “A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 47, pp. 3232-3248, December 2012.

•  Ping-Hsuan Hsieh, Jay Maxey, and Chih-Kong Ken Yang, “A phase-selecting digital phase-locked loop with bandwidth tracking in 65-nm CMOS technology,” IEEE Journal of Solid-State Circuits, vol.45, pp. 781-792, April 2010.

•  Ping-Hsuan Hsieh, Jay Maxey, and Chih-Kong Ken Yang, “Minimizing the supply sensitivity of a CMOS ring oscillator through jointly biasing the supply and control voltages,” IEEE Journal of Solid-State Circuits, vol. 44, pp. 2488-2495, September 2009.

•  Ping-Hsuan Hsieh and Chih-Kong Ken Yang, “Technique to reduce the resolution requirement of digitally controlled oscillators for digital PLLs,” IEEE Transactions on Circuits and Systems II, vol. 54, pp. 237-241, March 2007.