8.
Register-Transfer Design
@Topic
-
In
designing ASICs and processor, we group those components into control units
and datapath.
-
To
synthesize register-transfer design we introduce the model of an FSM with
a datapath (FSMD)
8.1
Design Model
-
Design Model (
P321 )
-
Contol input signal
* external signal
* status signal
8.2
FSMD Definition
-
One's counter specification
( P323 )
-
FSM were define as quintuple
< S, I, O, f, h > ( P323
)
-
FSMD specication of one's
counter ( P327 | P328
)
8.3
Algorithmic-State-Machine Charts
-
FSMD can specify by state-action
table or ASM chart
-
ASM symbles
( P329 )
-
Two-rule for specify FSMD
with ASM chart
1) The chart
must define a unique next state for each state
and set of conditions.
2) Every path
defined by the network of condition boxes must
lead to another state.
-
Ill-defined ASM chart
( P331A )
-
ASM chart for one's counter
( P331B )
-
ASM chart for one's counter
(custom design) ( P333
)
-
State-action table for
one's counter ( P334
| P336A | P336B )
-
Logic shematics for one's
counter ( P335 )
8.4
Synthesis From ASM Charts
-
RT Imp defines both a
control unit and a datapath
-
Datapath component
1) Storage Component
2) Function Units
( perform arithmetic, logic, and shift operations )
3) Buses
-
In an FSMD model :
The datapath is defined
by the variable assignments
that are executed
in its various states
-
Three basic optimization
techniques :
1) Register Sharing
( Variable Merging )
2) Function-Unit Sharing
( Operator Merging )
3) Bus Sharing ( Connection
Merging )
-
e.g. Small custom ASIC
:
Input two signed integer
a , b
Output
sqrt (a^2 + b^2) = max ((0.875x + 0.5y), x)
where x = max
(|a|, |b|)
y = min (|a|, |b|)
-
Square-root approximation
( P338)
-
Resource use in Square-root
approximation ( P339
)
-
Simple library components
( P341 )
-
Connectivity table
( P342 )
8.5
Register Sharing (Variable Merging)
-
We can group variables
that have nonoverlapping
lifetimes
and assign each group
to a single register
-
Left-edge algorithm
( P343 )
-
Register sharing generated
by Left-edge algorithm (
P338 | P344 )
-
Merging variables
with common sources
and destinations ( P345
)
-
Graph-partioning algorithm
( P346 )
-
Graph-partioning algorithm
for SRA ( P347 )
-
Register assignmented
by Graph-partioning algorithm ( P348
)
8.6
Functional Unit Sharing (Operator Merging)
-
Functional Unit Sharing
( P349 )
-
Complex library components
( P350 )
-
Operator merging for SRA
implementation ( P352
)
-
Datapath connectivity
( P353 )
-
Priorities in unit merging
( P354 )
-
Graph partitioning for
SRA datapath
-
SRA datapath obtained
( P355 )
by using prioritized
partitioning ( P356
)
8.7
Bus Sharing (Connection Merging)
-
Connection
source : output of reg & func unit
-
Connection
destination : input of reg & func unit
-
Connection
merging in SRA datapath ( P358
| P359 )
8.8
Register Merging
8.9
Chaining And Multicycling
-
SRA datapath with chained
units ( P363 )
-
SRA datapath with multicycle
units ( P364 )
8.10
Functional Unit Pipelining
-
Pipelined arithmetic unit
( P365 )
-
SRA datapath with single
AU ( P366A | P366B
)
-
Datapath with pipelined
functional units ( P367
)
8.11
ASM Pipelining
-
Datapath pipelining
( P369 | P370 )
-
Timing diagram for
datapath pipeline
with pipelined units ( P371
)
8.12
Control-Pipelining
-
Pipelined FSMD implementation
( P373 )
-
ASM charts for pipelined
implementation ( P374
)
8.13
Scheduling
-
Control/data flow graph
for SRA ( P376 )
-
Basic schedules
( P378 )
-
List-scheduling algorithm
( P379 )
-
Resource-constrained scheduling
( P380 )
-
Time-constrained scheduling
( P381 )
-
TC schedule for SRA algorithm
( P382 )
-
Probability distribution
graph
before, during, and
after TC scheduling ( P383
)
8.14
Chapter Summary
8.15
Further Readings
8.16
Problems
-
8.2
-
8.3
-
Design
one's counter by Xilinx
