Hsu, Charles Ching-Hsiang (徐清祥)

Professor

Ph. D., University of Illinois, Urbana-Champaign, USA, 1988

Flash memory

Power semiconductor devices

E-mail: chhsu@ee.nthu.edu.tw

　

Dr. Charles Ching-Hsiang Hsu received the B.S. degree from the National Tsing-Hua University (NTHU), Hsinchu, Taiwan, R.O.C., and the Ph.D. degree in electrical engineering from the University of Illinois, Urbana-Champaign, in 1981 and 1988, respectively. From 1983 to 1987, he worked on the generation, charging and annealing of electronic defect and hydrogenation effects in silicon MOS microstructure as a Graduate Research Assistant at the University of Illinois. In 1987, he joined the IBM T.J. Watson Research Center, Yorktown Heights, NY, where he co-developed p-type polysilicon gate for 0.25- and 0.1��m CMOS and worked on p-channel flash memory. In 1992, he joined the Department of Electrical Engineering, NTHU, and became a Professor in 1996. He has published papers on the topics of sub-0.5��m CMOS device reliability and modeling, 0.25-��m CMOS with dual gate processes, low-temperature CMOS, 0.1-��m CMOS, and flash memory. He has more than 20 patents. His current research interests are in flash memory, power semiconductor devices and analog application using bipolar-CMOS-DMOS (ABCD) integrated technology. Dr. Hsu received the Young Active Scientist Award from the Conference of Solid State Devices and Materials, Japan, in 1992. In 1995, he received an Excellent Youth Award from the Electronics Materials and Devices Association, Taiwan. In 1996, he and his students received the Best Paper Award from the International Electron Devices and Materials Symposium, Taiwan. In 1997, he received the award of Excellent Contribution in Industry Cooperation from the Ministry of Education and Excellent Research Award from the National Science Council.

　

Recent Publications

Journal Papers

  1. S.-J. Shen , C.-S. Yang , W.-J. Wong, Y.-S. Wang , C.-J. Lin , M.-S. Liang and C. C.-H. Hsu, "Degradation of flash memory using drain avalanche hot electron (DAHE) self convergence operation scheme," Jpn. J. Appl. Phys., Vol. 37, pp. L778-L780, 1998.

  2. W.-T. Sun, M.-C. Liaw, K.-C. Hsieh and C. C.-H. Hsu, "Impact of Nitrogen (N2+) implantation into polysilicon gate on thermal stability of cobalt silicide formed on polysilicon gate," IEEE Trans. on Electron Devices, No.9, 1998.

  3. W.-T. Sun, M.-C. Liaw and C. C.-H. Hsu, "Suppression of cobalt silicide agglomeration using nitrogen implantation," IEEE Electron Device Letters, Vol. 37, pp. 796-800, 1998.

  4. S.-J. Shen, C.-J. Lin and C. C.-H. Hsu, "High speed F-N operated volatile memory cell with stacked PECVD Nanocrystalline Si layer structure," Jpn. J. Appl. Phys., Vol. 37, No. 12B, pp. L1517-L1519 ,1998.

  5. S.-J. Shen, C. C.-H. Hsu and M.-S. Liang, "Optimization of program window from understanding of novel fast charge loss in nonvolatile memory," Jpn. J of Appl. Phys., 1998.

  6. W.-T. Sun, M.-C. Liaw and C. C.-H. Hsu, "Mechanism of improved thermal stability of cobalt silicide formed on polysilicon gate by Nitrogen (N2+) implantation," Jpn. J. of Appl. Phys., 1998.

  7. S.-J. Shen, C.-S. Yang, Y.-S. Wang and C. C.-H. Hsu, "A self-convergent programming scheme for multi-level P-channel flash memory," Jpn. J. Appl. Phys., 1998.

  8. C.-S. Yang, W.-J. Wong, S.-J. Shen, Y.-S. Wang and C. C.-H. Hsu, "New self-convergent programming method for multi-level and type flash memory," Jpn. J. Appl. Phys., Vol.38, Pt. 1, No. 4B, pp. 47-51, 1999.

  9. C.-S. Yang, C.-J. Liu, M.-C. Liaw, T.-S. Chao and C. C.-H. Hsu, "Novel Bi-directional tunneling program/erase NOR (BiNOR) type flash EEPROM," IEEE Trans. on Electron Device, Vol. 46, No. 6, pp. 1294-1296, 1999.

  10. F. R.-L. Lin, M.-L. Lee, S.-Y. Lin, C.-H. Boe, C.-P. Yeh, P.-H. Wu, W.-S. Wang, J. Ni and C.C.-H. Hsu, “A novel high-density and high-speed NAND-type electrical erasable programmable read only memory,” Jpn. J. Appl. Phys., Vol. 39, Pt. 1, No. 4B, pp. 2208-2214, 2000.

  11. A.H.-F. Chou, E.C.-S. Yang, W.-Z. Wong, Y.-C. King and C.C.-H. Hsu, “A new bit-line-controlled self-convergent multilevel and-type flash memory,” Jpn. J. Appl. Phys., Vol. 39, Pt. 1, No. 4B, pp. 2215-2218, 2000.

  12. A.H.-F. Chou, W.-Z. Wong, E.C.-S. Yang, Y.-Y. Yao, Y.-S. Wang, Y.-C. King and C.C.-H. Hsu, “ Comprehensive study of a new self-convergent programming scheme for split gate flash memory,” Jpn. J. Appl. Phys., Vol. 39, Pt. 1, No. 4B, pp. 2219-2222, 2000.

  13. R.-L. Lin, T. Chang, A.C. Wang and C.C.-H. Hsu, “New self-adjusted dynamic source multilevel P-channel flash memory,” IEEE Trans. on Electron Device, Vol. 47, No. 4, pp. 841-847, 2000.

  14. F.R.-L. Lin, S.-Y. Lin, M.-L. Lee, C.-H. Boe, C.-P. Yeh, P.-H. Wu, J. Ni, Y.-C. King and C.C.-H. Hsu, “Novel source-controlled self-verified programming for multilevel EEPROM’s,” IEEE Trans. on Electron Device, Vol. 47, No. 6, pp. 1166-1174, 2000.

Conference Papers

  1. Y.-S. Wang, S.-J. Shen, C.-S. Yang and C. C.-H. Hsu, "New programming scheme for P-channel flash memory," IEEE Nonvolatile Semiconductor Memory Workshop (IEEE NVSMW 98’), pp. 88-91,1998.

  2. W.-T. Sun, M.-C. Liaw and C. C.-H. Hsu, "Using Nitrogen (N2+) implantation to suppress the agglomeration of cobalt silicide on Poly-Si gate," The fifth symposium on Nano Device Technology (SNDT’98), pp. 14, 1998.

  3. (invited) C. C.-H. Hsu, "New programming scheme for P-channel flash memory," IEEE Nonvolatile Semiconductor Memory Workshop (IEEE NMW 98’), pp. 27-34, 1998.

  4. Y.-S. Wang, S.-J. Shen, C.-S. Yang and C. C.-H. Hsu, "New programming scheme for P-channel flash memory," IEEE Nonvolatile Semiconductor Memory Work shop (IEEE NSMW 98’), 1998.

  5. (invited) R.-L. Lin, Y.-S. Wang and C. C.-H. Hsu, "P-channel flash memory," IEEE Nonvolatile Semiconductor Memory Workshop (IEEE NSMW 98’), 1998.

  6. C.-S. Yang, W.-J. Wong, S.-J. Shen, Y.-S Wang and C. C.-H. Hsu, "New self-convergent programming method for multi-level and flash memory," International Conference on Solid State Devices and Materials (SSDM98’), 1998.

  7. C.-W. Hsu, S.-C. Wang, Z.-M. Chau, S.-J. Chang, C.-S. Yang and C. C.-H. Hsu, "An insight of the correlation between constant current, ramp current, and ramp voltage stresses on MOS reliability," International Electron Device and Material Symposia (IEDMS), 1998.

  8. H.-M. Lee, Y.-S. Wang, S.-J. Shen, C.-S. Yang and C. C.-H. Hsu, "Constant current programming scheme for P-channel flash memory," International Electron Device and Material Symposia (IEDMS), 1998.

  9. C.-S. Yang, C.-J. Liu, T.-S. Chao, M.-C. Liaw and C. C.-H. Hsu, "Novel Bi-directional tunneling program/erase NOR (BiNOR) type flash EEPROM," Proc. of International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), 1999.

  10. C.-S. Yang, C.-J. Liu, T.-S. Chao, M.-C. Liaw and C. C.-H. Hsu, "Novel Bi-Directional tunneling NOR (BiNOR) type 3-D flash memory cell," VLSI Tech. Dig., 1999.

  11. H.-F. Chou, C.-S. Yang, W.-J. Wong and C.C-H. Hsu, "A new bit-line-controlled self-convergent multi-level and-type flash memory," International Conference on Solid State Devices and Materials (SSDM’99), pp. 536, 1999.

  12. W.-J. Wong, E. C.-S. Yang, A. H.-F. Chou, Y.-Y. Yao, Y.-S. Wang and C. C-H. Hsu, "Comprehensive study of a new self-convergent programming scheme for split gate flash memory," International Conference on Solid State Devices and Materials (SSDM’99), pp. 540, 1999.

  13. R.-L. Lin, M.-L. Lee, S.-Y. Lin, C.-H. Boe, C. C.-H. Hsu, C.-P. Yeh, P.-H. Wu, W.-S. Wang and J. Ni, "A novel high-density and high-speed NAND-type EEPROM," International Conference on Solid State Devices and Materials (SSDM’99).

  14. R.-L. Lin, C.-H. Poe, C. C.-H. Hsu, C.-P. Yeh, P.H. Wu and J. Ni, "A novel hot carrier mechanism: band-to-band tunneling hole induced bipolar hot electron (BBHBHE)," International Electron Device and Material Symposia (IEDMS), 1999.

  15. F.R.-L. Lin, C.-H. Poe, C.-P. Yeh, P.-H. Wu, J. Ni and C.C.-H.Hsu, “A novel carrier mechanism: band-to-band tunneling hole induced bipolar hot electron (BBHBHE),” Electron Devices Meeting, 1999. IEDM Technical Digest. International, 1999, pp. 741-744.

  16. A.H.-F. Chou, Y.-Y. Yao, W.-Z. Wong, E.C.-S. Yang, Y.-S. Wong, Y.-C. King and C.C.-H. Hsu, “New coupling ratio extraction method for split gate flash memory,” IEEE Nonvolatile Semiconductor Memory Workshop, 2000.

Patents

  1. US Patent No. 5679591, 1997, ”Method of making raised-bitline contactless trenched flash memory cell”, by R.-L. Lin, C. C-H. Hsu, M.-S. Liang.

  2. US Patent No. 5714412, 1997, ”Multi-level, split gate, flash memory cell and method of manufacture thereof”, by M.-S. Liang, D.-S. Kuo, C. C-H. Hsu, R.-L. Lin.

  3. US Patent No. 5834806, 1998, “Raised-bitline, contactless, trenched, flash memory cell”, by R.-L. Lin, C. C.-H. Hsu, M.-S. Liang.

  4. US Patent No. 5851881, 1998, “Method of making monos flash memory for multi-level logic”, by R.L. Lin, C. C-H. Hsu, M.-S. Liang.

  5. US Patent No. 5861634, 1999, “Charge collector structure for detecting radiation induced charge during integrated circuit processing”, by C. C-H Hsu, C.-J. Lin and M.-S. Liang.

  6. ROC Patent No. 088648, 1997, “極快速擬動態非揮發性快閃記憶體之陣列結構與其執行編碼時臨界電壓自我校正方法”,林瑞霖,徐清祥。

  7. ROC Patent No. 089052, 1997, “絕緣閘雙極電晶體之射極的製造方法”,林瑞霖,徐清祥。

  8. ROC Patent No. 091848, 1997, “快閃記憶體之編碼操作模式”,林瑞霖,徐清祥。

Book Chapter

  1. S.-J. Shen, F.R.-L. Lin, A.H.-F. Chou, E.C.-S.Yang and C.C.-H. Hsu, "Flash Memories" in The VLSI Handbook, CRC Press LLC, 1999.