|
CC Hsieh’s Publication List |
|
國際期刊 (International
Journal) |
|
[1]
Tzu-Hsiang
Hsu, Guan-Cheng Chen, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong
Tang, Meng-Fan Chang, and Chih-Cheng
Hsieh, “A 0.8 V Intelligent Vision Sensor With
Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode
Processing-in-Sensor Technique for Image Classification,” IEEE Journal of
Solid-State Circuits, vol 58, no. 11, pp. 3266-3274, Nov. 2023. [2]
Min-Yang
Chiu, Guan-Cheng Chen, Tzu-Hsiang Hsu, Ren-Shuo Liu, Chung-Chuan Lo,
Kea-Tiong Tang, Meng-Fan Chang, and Chih-Cheng
Hsieh, “A Multi-Mode Vision Sensor with Temporal Contrast Pixel and
Column-Parallel Local Binary Pattern Extraction for Dynamic Depth Sensing
Using Stereo Vision,” IEEE Journal of Solid-State Circuits, vol 58,
no. 10, pp. 2767-2777, Oct. 2023. [3]
Chih-Cheng
Chen, Yu-Hsiang Huang, John Carl Joel S. Marquez, and Chih-Cheng Hsieh, “A 12-ENOB Second-Order Noise Shaping
SAR ADC with PVT-insensitive Voltage-Time-Voltage Converter,” IEEE Journal
of Solid-State Circuits, vol 58, no. 10, pp. 2897-2906, Oct. 2023. [4]
Jian-Wei
Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung
Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Tianlong Pan,
Chuan-Jia Jhang, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li,
Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo,
Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh,
Kea-Tiong Tang, Meng-Fan Chang, "A 8-b-Precision 6T SRAM
Computing-in-Memory Macro Using Segmented-Bitline
Charge-Sharing Scheme for AI Edge Chips," IEEE Journal of Solid-State
Circuits, vol 58, no. 1, pp. 303-315, Jan. 2023. [5]
Je-Min
Hung, Tai-Hao Wen, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Chin-I
Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng
Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan
Chang, "8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using
Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices," IEEE
Journal of Solid-State Circuits, vol 58, no. 1, pp. 303-315, Jan. 2023. [6]
Syuan-Hao Sie, Jye-Luen
Lee, Yi-Ren Chen, Zuo-wei Yeh, Zhaofang
Li, Chih-Cheng Lu, Chih-Cheng Hsieh,
Meng-Fan Chang, Kea-Tiong Tang, "MARS: Multi-macro
Architecture SRAM CIM-Based Accelerator with Co-designed Compressed
Neural Networks," IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, vol 41, no. 5, pp. 1550-1562, May. 2022. [7]
Jian-Wei
Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang,
Yen-Lin Chung, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Hongwu Jiang, Shanshi Huang, Sih-Han Li, Shyh-Shyuan
Sheu, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shimeng
Yu, Meng-Fan Chang, "Two-Way Transpose Multibit 6T SRAM
Computing-in-Memory Macro for Inference-Training AI Edge Chips," IEEE
Journal of Solid-State Circuits, vol 57, no. 2, pp. 609-624, Feb. 2022. [8]
Xin
Si , Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su, Pei-Jung Lu, Jing-Hong Wang,
Ta-Wei Liu, Ssu-Yen Wu, Ruhui
Liu, Yen-Chi Chou, Yen-Lin Chung, William Shih, Chung-Chuan Lo, Ren-Shuo Liu,
Chih-Cheng Hsieh, Kea-Tiong Tang,
Nan-Chun Lien, Wei-Chiang Shih, Yajuan He, Qiang
Li, Meng-Fan Chang, “A Local Computing Cell and 6T SRAM based
Computing-in-Memory Macro with 8b MAC Operation for Edge AI Chips,” IEEE
Journal of Solid-State Circuits, vol 56, no. 9, pp. 2817-2831, Sep. 2021. [9]
Tzu-Hsiang
Hsu, Yen-Kai Chen, Min-Yang Chiu, Guan-Cheng Chen, Ren-Shuo Liu, Chung-Chuan
Lo, Kea-Tiong Tang, Meng-Fan Chang, and Chih-Cheng
Hsieh, “A 0.8V Multimode Vision Sensor for Motion and Saliency
Detection with Ping-Pong PWM Pixel,” IEEE Journal of Solid-State Circuits,
vol 56, no. 8, pp. 2516-2524, Aug. 2021. [10]
Tzu-Hsiang
Hsu, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan
Chang, Chih-Cheng Hsieh,
"A 0.5V Real-Time Computational CMOS Image Sensor with Programmable
Kernel for Feature Extraction," IEEE Journal of Solid-State Circuits,
vol 56, no. 5, pp.
1588-1596, May. 2021. [11]
Yen-Cheng
Chiu, Zhixiao Zhang, Jia-Jing Chen, Xin Si, Ruhui Liu, Yung-Ning Tu, Jian-Wei Su, Wei-Hsing Huang,
Jing-Hong Wang, Wei-Chen Wei, Je-Min Hung, Shyh-Shyuan
Sheu, Sih-Han Li, Chih-I Wu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang, “A 4-Kb
1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for
CNN-Based AI Edge Processors,” IEEE Journal of Solid-State Circuits, vol
55, no. 10, pp. 2790-2801, Oct. 2020. [12]
Xin
Si, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng
Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun, Rui
Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang,
“A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI
Edge Processors,” IEEE Journal of Solid-State Circuits, vol 55, no. 1,
pp. 189-202, Jan. 2020. [13]
Cheng-Xin
Xue, Wei-Hao Chen, Je-Syu Liu, Jia-Fang Li, Wei-Yu
Lin, Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Tsung-Yuan Huang, Ting-Wei
Chang, Tung-Cheng Chang, Hui-Yao Kao, Yen-Cheng Chiu, Chun-Ying Lee, Ya-Chin
King, Chrong-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan
Chang, "Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With
Multibit Input and Weight for CNN-Based AI Edge Processors," IEEE
Journal of Solid-State Circuits, vol 55, no. 1, pp. 203-215, Jan. 2020. [14]
Kwuang-Han Chang and Chih-Cheng Hsieh, "A
Calibration-Free 13-bit 10-MS/s Full-Analog SAR ADC With Continuous-Time
Feedforward Cascaded (CTFC) Op-Amps," IEEE Journal of Solid-State
Circuits, vol 54, no. 10, pp. 2691-2702, Oct. 2019. [15]
Wei-Hao
Chen, Chunmeng Dou, Kai-Xiang Li, Wei-Yu Lin,
Pin-Yi Li, Jian-Hao Huang, Jing-Hong Wang, Wei-Chen Wei, Cheng-Xin Xue,
Yen-Cheng Chiu, Ya-Chin King, Chorng-Jung Lin,
Ren-Shuo Liu, Chih-Cheng Hsieh,
Kea-Tiong Tang, J. Joshua Yang, Mon-Shu Ho, Meng-Fan Chang,
CMOS-integrated memristive non-volatile
computing-in-memory for AI edge processors, Nature Electronics, vol. 2, pp. 420-428, Aug. 2019. [16]
Kwuang-Han Chang and Chih-Cheng Hsieh, "A
Calibration-Free 12-bit 50-MS/s Full-Analog SAR ADC With Feedback
Zero-Crossing Detectors," IEEE Journal of Solid-State Circuits, vol
54, no. 6, pp. 1624-1635, June. 2019. [17]
Sung-En
Hsieh, and Chih-Cheng Hsieh,
"A 0.4 V 13-bit 270 kS/s SAR-ISDM ADC with Opamp-Less Time-Domain Integrator," IEEE Journal
of Solid-State Circuits, vol 54, no. 6, pp. 1648-1686, June. 2019. [18]
Albert
Yen-Chih Chiou, and Chih-Cheng
Hsieh, "An ULV PWM CMOS Imager with Adaptive-Multiple-Sampling
Linear Response, HDR Imaging, and Energy Harvesting," IEEE Journal of
Solid-State Circuits, vol 54, no. 1, pp. 298-306, Jan. 2019. [19]
Sung-En
Hsieh, Chen-Che Kao, and Chih-Cheng
Hsieh, "A 0.5V 12-bit SAR ADC using Adaptive Time-Domain
Comparator with Noise Optimization," IEEE Journal of Solid-State
Circuits, vol 53, no. 10, pp. 2763-2771, Oct. 2018. [20]
Ting-I
Chou, Kwuang-Han Chang, Jia-Yin Jhang, Shih-Wen
Chiu, Guoxing Wang, Chia-Hsiang Yang, Herming Chiueh, Hsin Chen, Chih-Cheng Hsieh, Meng-Fan Chang,
Kea-Tiong Tang*, A 1V 2.6mW Environmental Compensated Fully Integrated
Nose-on-a-Chip, IEEE Transaction on
Circuits and Systems II: Express Briefs (TCAS-II), vol. 65, no. 10,
pp.1365-1369, Oct 2018. [21]
Tzu-Hsiang
Hsu, Ting Liao, Nien-An Lee, and Chih-Cheng Hsieh, "A CMOS
Time-of-Flight Depth Image Sensor With In-Pixel Background Light Cancellation
and Phase Shifting Readout Technique," IEEE Journal of Solid-State
Circuits, vol 53, no. 10, pp. 2898-2905, Oct. 2018. [22]
Sung-En
Hsieh and Chih-Cheng Hsieh,
"A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting
DAC," IEEE Journal of Solid-State Circuits, vol 53, no. 9, pp.
2595-2603, Sept. 2018. [23]
Kwuang-Han Chang and Chih-Cheng Hsieh, "A
12-bit 150-MS/s Sub-Radix-3 SAR ADC with Switching Miller Capacitance
Reduction," IEEE Journal of Solid-State Circuits, vol 53, no. 6,
pp. 1755-1764, June. 2018. [24]
Kwuang-Han Chang and Chih-Cheng Hsieh, "A
Hybrid Analog-to-Digital Conversion Algorithm with Sub-radix and Multiple
Quantization Thresholds," IEEE
Transaction on Circuits and Systems V I, vol. 64, no. 6, pp. 1400-1408, June. 2017. [25]
Chin
Yin, Kuan-Lin Liu, Chin-Fong Chiu, and and Chih-Cheng Hsieh, " A
32-stage 15-bit Digital Time Delay Integration Linear CMOS Image Sensor with
Data Prediction Switching Technique," IEEE Transaction on Electron
Devices, vol. 64, no. 3, pp.
1167-1173, Mar. 2017. [26]
Jin-Yi
Lin and Chih-Cheng Hsieh,
" A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90 nm CMOS," IEEE
Transaction on Circuits and Systems VI, vol. 64, no. 3, pp. 562-572, Mar. 2017. [27]
Pei-Chen
Lee, Jin-Yi Lin, and Chih-Cheng
Hsieh, " A 0.4 V 1.94 fJ/conversion-step
10-bit 750 kS/s SAR ADC with Input-Range-Adaptive
Switching," IEEE Transaction on Circuits and Systems VI, vol. 63, no. 12, pp. 2149-2157, Dec. 2016. [28]
Sung-En
Hsieh and Chih-Cheng Hsieh,
" A 0.3V 0.705fJ/Conversion-step 10-bit SAR ADC with Shifted Monotonic
Switching Procedure in 90nm CMOS," IEEE Transaction on Circuits and
Systems V II, vol. 63, no. 12,
pp. 1171-1175, Dec. 2016. [29]
Albert
Yen-Chih Chiou and Chih-Cheng Hsieh,
" A 137dB Dynamic Range and 0.32V Self-Powered CMOS Imager with Energy
Harvesting Pixels," IEEE Journal of Solid-State Circuits, vol 51,
no. 11, pp. 2769-2776, Nov. 2016. [30]
Pei-Yi
Lai Lee, Chih-Wen Lu, Chih-Cheng
Hsieh, Tsin-Yuan Chang, Jenny Yi-Chun Liu, Hsin-Chin Liang,
Hsiang-Ning Wu, Electric Hum Signal Readout Circuit for Touch Screen Panel
Applications, Journal of Display
Technology, vol. 12, no. 11, pp. 1444-145, Nov. 2016. [31]
Chin
Yin, Chin-Fong Chiu, and Chih-Cheng
Hsieh, " A 0.5 V, 14.28 kfps, 109 dB
Smart Image Sensor With Array-Level Image Signal
Processing for IoT Applications," IEEE Transaction on Electron
Devices, vol. 63, no. 3, pp.
1134-1140, Mar. 2016. [32]
Yan-Jiun
Chen, Kwuang-Han Chang, and Chih-Cheng Hsieh, "A 2.02V5.16 fJ/Conversion-step
10-Bit Hybrid Coarse-Fine SAR ADC With Time-domain Quantizer in 90-nm
CMOS," IEEE Journal of Solid-State Circuits, vol. 51, no. 2, pp. 357-364, Feb. 2016. [33]
Chih-Lin
Lee, and Chih-Cheng Hsieh,
A 0.5 V/1.8 V High Dynamic Range CMOS Imager for Artificial Retina
Applications, IEEE Sensors Journal, vol. 15, no. 12, pp. 1625-1632, Dec. 2015. [34]
Jin-Yi
Lin and Chih-Cheng Hsieh, A
0.3V 10-bit 1.17f SAR ADC with Merge and Split Switching in 90nm CMOS,
IEEE Transaction on Circuits and Systems V I, vol.
62, no. 1, pp. 70-79, Jan. 2015. [35]
Shih-Wen
Chiu, Jen-Huo Wang, Kwuang-Han Chang, Ting-Hau
Chang, Chia-Min Wang, Chia-Lin Chang, Chen-Ting Tang, Chien-Fu Chen,
Chung-Hung Shih, Han-Wen Kuo, Li-Chun Wang, Hsin Chen, Chih-Cheng Hsieh, Meng-Fan Chang, Yi-Wen Liu, Tsan-Jieh Chen, Chia-Hsiang Yang, Herming
Chiueh, Juyo-Min Shyu,
Kea-Tong Tang, A Fully Integrated Nose-on-a-Chip for Rapid
Diagnosis of Ventilator-Associated Pneumonia, IEEE Transaction
on Biomedical Circuits and Systems, vol. 8, no. 6, pp. 765-778, Dec. 2014. [36]
Wei-Fan
Chou, Shang-Fu Yeh, Chin-Fong Chiu, and Chih-Cheng
Hsieh, A Linear-Logarithmic CMOS Image Sensor with Pixel-FPN
Reduction and Tunable Response Curve, IEEE Sensors Journal, vol. 14, no. 5, pp. 1625-1632, May 2014. [37]
Meng-Ting
Chung, Chih-Lin Lee, Chin Yin, and Chih-Cheng
Hsieh, A 0.5 V PWM CMOS Imager with 82 dB Dynamic Range and 0.055%
Fixed-Pattern-Noise, IEEE Journal of Solid-State Circuits, vol. 48, no. 10, pp. 2522-2530, Oct.
2013. [38]
Chi-Ying
Lee, Chih-Cheng Hsieh, and
Jenn-Chyou Bor, A 2.4-GHz 10-Mbps BFSK Embedded
Transmitter With a Stacked-LC DCO for Wireless
Testing Systems, IEEE Transactions on Very Large Scale Integration Systems,
vol. 21, no. 9, pp. 1727-1737, Sep. 2013 [39]
Shang-Fu
Yeh, and Chih-Cheng Hsieh,
and Ka-Yi Yeh, A 3 megapixel 100Fps 2.8gm Pixel Pitch CMOS Image Sensor Layer
with Built-in Self-test for 3D Integrated Imagers, IEEE Journal of
Solid-State Circuits, vol. 48,
no. 3, pp. 839-849, Mar. 2013. [40]
Chih-Lin
Lee, and Chih-Cheng Hsieh,
A 0.8V 4096 Pixels CMOS Sense-and-Stimulus Imager for Retinal Prosthesis, IEEE
Transaction on Electron Devices,
vol. 60, no. 3, pp. 1162-1168, Mar. 2013. [41]
Shang-Fu
Yeh, and Chih-Cheng Hsieh,
A Novel Single Slope ADC Design for Full Well Capacity Expansion of CMOS
Image Sensor, IEEE Sensors Journal, vol. 13, no. 3, pp. 1012-1017, Mar. 2013. [42]
Wei-Lin
Chen, and Chih-Cheng Hsieh,
Exploration of Second-Order Effects in High-Performance Continuous-Time UG
Modulators Using Discrete-Time Models, IEEE Transaction on Circuits and
Systems V I, vol. 59, no. 12,
pp. 2890-2900, Dec. 2012. [43]
Tsan-Jieh Chen, Herming Chiueh, Chih-Cheng
Hsieh*, Chin Yin, Wen-Hsu Chang, Hann-Huei Tsai, and Chin-Fong Chiu, A
High Definition Image Pre-Processing System for Multi-Stripe Satellites Image
Sensors, IEEE Sensors Journal,
vol. 12, no. 9, pp. 2859-2865, Sep. 2012. [44]
Shang-Fu
Yeh, Chih-Cheng Hsieh,
Chiao-Jen Cheng, and Chun-Kai Liu, A Dual-Exposure Single-Capture Wide
Dynamic Range CMOS Image Sensor with Column-Wise Highly/Lowly-Illuminated
Pixel Detection, IEEE Transaction on Electron Devices, vol. 59, no. 7, pp. 1948-1955, July 2012. [45]
Kea-Tiong
Tang,
Shih-Wen Chiu, Meng-Fan Chang*, Chih-Cheng
Hsieh*, and Juyo-Min Shyu*, A
Low-Power Electronic Nose Signal Processing Chip for a Portable Artificial
Olfaction System, IEEE Transaction on Biomedical Circuits and Systems,
vol. 5, no. 4, pp. 380-390, Aug. 2011. [46]
Chung-Yu Wu*; Yu-Chuan Shih; Jeng-Feng Lan; Chih-Cheng Hsieh; Chien- Chang Huang; Jr-Houng Lu; Design,
Optimization, and Performance Analysis of New Photodiode Structures for CMOS
Active-Pixel-Sensor (APS) Imager Applications, IEEE Sensor Journal, vol. 4, no. 1, pp. 135-144, Feb. 2004. [47]
Chih-Cheng
Hsieh, Chung-Yu Wu*, Tai-Ping Sun, Far-Wen Jih; and Ya-Tung Cherng,
High-performance CMOS buffered gate modulation input (BGMI) readout circuits
for IR FPA, IEEE Journal of Solid-State
Circuits, vol. 33, no. 8, pp. 1188-1198, Aug. 1998. [48]
Chih-Cheng
Hsieh, Chung-Yu Wu* and Tai-Ping Sun, A New Cryogenic CMOS Readout
Structure for Infrared Focal Plane Array, IEEE
Journal of Solid-State Circuits, vol. 32, no. 8, pp. 1192-1199, Aug.
1997. [49]
Chih-Cheng
Hsieh, Chung-Yu Wu*, Far-Wen Jih and Tai-Ping Sun, Focal-Plane-Arrays
and CMOS Readout Techniques of Infrared Imaging Systems, IEEE Trans. on Circuits and Systems for Video Technology, vol. 7,
no. 4, pp. 594-605, Aug. 1997. [50]
Chung-Yu Wu* and Chih-Cheng
Hsieh, New Design Techniques for a Complementary Metal-Oxide
Semiconductor Current Readout Integration Circuit for Infrared Detector
arrays, Optical Engineering, vol.
34, no. 1, pp. 160-168, Jan. 1995. |
|
國際會議 (International
Conference) |
|
[1]
[Invited
Forum Talk] Chih-Cheng Hsieh, Intelligent
Imager with Processing-in-Sensor Techniques, IEEE International Solid-State Circuits Conference (ISSCC), Feb.
2024. [2]
W-S.
Khwa, P-C. Wu, J-J. Wu, J-W. Su, H-Y. Chen, Z-E. Ke,
T-C. Chiu, J-M. Hsu, C-Y. Cheng, Y-C. Chen, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, M-F.
Chang, A 16nm 96Kb Integer-Floating-Point Dual-Mode
Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and
33.2-91.2TFLOPS/W for AI-Edge Devices, 2024 IEEE International Solid-State Circuits Conference (ISSCC), Feb.
2024. [3]
T-H.
Wen, H-H. Hsu, W-S. Khwa, W-H. Huang, Z-E. Ke, Y-H.
Chin, H-J. Wen, Y-C. Chang, W-T. Hsu, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, S-H. Teng, C-C. Chou, Y-D. Chih,
T-Y. J. Chang, M-F. Chang, A 22nm 16Mb Floating-Point ReRAM
Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices, 2024 IEEE International Solid-State Circuits
Conference (ISSCC), Feb. 2024. [4]
Hsin
Yu, John Carl Joel Salao Marquez, Chih-Cheng
Hsieh, A -20oC~+107oC 52mk-NETD
Reference-cell-free 15-bits ROIC for 80x60 Microbolometer Thermal Imager, 2023 Symposium on VLSI Technology and
Circuits (VLSI Symposium), June. 2023. [5]
Yu-Hsiang
Huang, Min-Ruei Wu, Chih-Cheng Hsieh, A CMOS Image Sensor With 1.6us
Conversion Time 10-bits Column-Parallel Hybrid ADC Using Self-Adaptive
Charge-Injection Cell, 2023
International Image Sensor Workshop (IISW), May. 2023. [6]
P-C.
Wu, J-W. Su, L-Y. Hong, J-S. Ren, C-H. Chien, H-Y. Chen, C-E. Ke, H-M. Hsiao,
S-H. Li, S-S. Sheu, W-C. Lo, S-C. Chang, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, M-F.
Chang, A 22-nm 832-kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute
Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices, 2023 IEEE International Solid-State
Circuits Conference (ISSCC), Feb. 2023. [7]
W-H.
Huang, T-H. Wen, J-M. Hung, W-S. Khwa, Y-C. Lo,
C-J. Jhang, H-H. Hsu, Y-H. Chin, Y-C. Chen, C-C. Lo, R-S. Liu, K-T. Tang, Chih-Cheng Hsieh, Y-D. Chih, T-Y.
Chang, M-F. Chang, A Nonvolatile AI-Edge Processor with 4MB SLC-MLC
Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W, 2023 IEEE International Solid-State
Circuits Conference (ISSCC), Feb. 2023. [8]
Y-C.
Chiu, W-S. Khwa, C-Y. Li, F-L. Hsieh, Y-A. Chien,
G-Y. Lin, P-J. Chen, T-H. Pan, D-Q. You, F-Y. Chen, A. Lee, C-C. Lo, R-S.
Liu, Chih-Cheng Hsieh, K-T. Tang,
Y-D. Chih, T-Y. Chang, M-F. Chang, A 22-nm 8-Mb 46.4-160.1-TOPS/W
STT-MRAM Near-Memory-Computing Macro with 8b precision for AI-edge Devices, 2023 IEEE International Solid-State
Circuits Conference (ISSCC), Feb. 2023. [9]
Min-Yang
Chiu, Guan-Cheng Chen, Yu-Hsiang Huang, Tzu-Hsiang Hsu, Chung-Chuan Lo,
Ren-Shuo Liu, Meng-Fan Chang, Kea-Tiong Tang, Chih-Cheng Hsieh, A 0.56V/0.8V Vision Sensor with Temporal
Contrast Pixel and Column-Parallel Local Binary Pattern Extraction for
Dynamic Depth Sensing Using Stereo Vision, in 2021 IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2022. [10]
T-H.
Hsu, G-C. Chen, Y-R. Chen, C-C. Lo, R-S. Liu, M-F. Chang, K-T. Tang, Chih-Cheng Hsieh, A 0.8V
Intelligent Vision Sensor with Tiny Convolutional Neural Network and
Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for
Image Classification, 2022 IEEE
International Solid-State Circuits Conference (ISSCC), Feb. 2022. [11]
P-C.
Wu, J-W. Su, Y-L. Chung, L-Y. Hong, J-S. Ren, F-C. Chang, Y. Wu, H-Y. Chen,
C-H. Lin, H-M. Hsiao, S-H. Li, S-S. Sheu, S-C. Chang, W-C. Lo, C-C. Lo, R-S.
Liu, Chih-Cheng Hsieh, K-T. Tang,
C-I. Wu, M-F. Chang, A 28nm 1Mb Time-Domain Computing-in-Memory
6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC
Operations for Edge-AI Devices, 2022
IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022. [12]
J-M.
Hung, Y-H. Huang, S-P. Huang, F-C. Chang, T-H. Wen, C-I. Su, W-S. Khwa, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, Y-D. Chih, T-Y. J. Chang, M-F.
Chang, An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile
Computing-in-Memory Macro using Time-Space-Readout with 1286.4 - 21.6TOPS/W
for Edge-AI Devices, 2022 IEEE
International Solid-State Circuits Conference (ISSCC), Feb. 2022. [13]
Y-C.
Chiu, W-S. Khwa, C-S. Yang, S-H. Teng, H-Y. Huang,
F-C. Chang, Y. Wu, Y-A. Chien, F-L. Hsieh, C-Y. Li, G-Y. Lin, P-J. Chen, T-H.
Pan, C-C. Lo, R-S. Liu, Chih-Cheng
Hsieh, K-T. Tang, C-P. Lo, Y-D. Chih, T-Y. J. Chang, M-F. Chang, A
22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s
Read- and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations, 2022 IEEE International Solid-State
Circuits Conference (ISSCC), Feb. 2022. [14]
Chih-Cheng
Chen, Chih-Cheng Hsieh, A
12-ENOB Second-Order Noise Shaping SAR ADC with PVT-insensitive
Voltage-Time-Voltage Converter, in 2021
IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2021. [15]
Hsin-Yu
Wu, Wei-Tse Kao, Harrison Hao-Yu Ku, Cheng-Te Wang, Chih-Cheng
Hsieh, Ren-Shuo Liu, Kea-Tiong Tang, Chung-Chuan Lo, A
Bio-Inspired Motion Detection Circuit Model for the Computation of Optical
Flow: The Spatial-Temporal Filtering Reichardt Model, in 2021 IEEE 3rd International Conference on Artificial Intelligence
Circuits and Systems (AICAS), June. 2021. [16]
Wen-Chieh
Wu, Chen-Fu Yeh, Alexander James White, Cheng-Te
Wang, Zuo-Wei Yeh, Chih-Cheng Hsieh,
Ren-Shuo Liu, Kea-Tiong Tang, Chung-Chuan Lo, Integer Quadratic
Integrate-and-Fire (IQIF): A Neuron Model for Digital Neuromorphic Systems,
in 2021 IEEE 3rd International
Conference on Artificial Intelligence Circuits and Systems (AICAS), June.
2021. [17]
Wei-Chih
Lai, Tzu-Hsiang Hsu, Chih-Cheng Chen, Chih-Cheng
Hsieh, A 12-Bit SAR ADC with Reference Voltage Ripple Suppression, in 2021 IEEE International Symp. on Circuits
and Systems (ISCAS), May. 2021. [18]
C-X.
Xue, J-M. Hung, H-Y. Kao, Y-H. Huang, S-P. Huang, F-C. Chang, P. Chen, T-W.
Liu, C-J. Jhang, C-I. Su, W-S. Khwa, C-C. Lo, R-S.
Liu, Chih-Cheng Hsieh, K-T. Tang,
Y-D. Chih, T-Y. J. Chang, M-F. Chang, A 22nm 4Mb 8b-Precision ReRAM
Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices,
2021 IEEE International Solid-State
Circuits Conference (ISSCC), Feb. 2021. [19]
J-W.
Su, Y-C. Chou, R. Liu, T-W. Liu, P-J. Lu, P-C. Wu, Y-L. Chung, L-Y. Hung,
J-S. Ren, T. Pan, S-H. Li, S-C. Chang, S-S. Sheu, W-C. Lo, C-I. Wu, X. Si,
C-C. Lo, R-S. Liu, Chih-Cheng Hsieh,
K-T. Tang, M-F. Chang, A 28nm 384kb 6T-SRAM Computation-in-Memory
Macro with 8b of Precision for AI Edge Chips, 2021 IEEE International Solid-State Circuits Conference (ISSCC),
Feb. 2021. [20]
You-Shin
Chen, Tzu-Hsiang Hsu, Guan-Cheng Chen, Chien-Wen Chen, Chih-Cheng Hsieh, A Monolithic Optical Encoder Using CMOS
Image Sensor with Background Light Cancellation, 2020 IEEE International Symp. on Circuits and Systems (ISCAS), Oct. 2020. [21]
Tzu-Hsiang
Hsu, Yen-Kai Chen, Jun-Shen Wu, Wen-Chien Ting, Cheng-Te
Wang, Chen-Fu Yeh, Syuan-Hao Sie, Yi-Ren Chen,
Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh, A 0.8V
Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM
Pixel, 2020 IEEE International
Solid-State Circuits Conference (ISSCC), Feb. 2020. [22]
J-W.
Su, X. Si, Y-C. Chou, T-W. Chang, W-H. Huang, Y-N. Tu, R. Liu, P-J. Lu, T-W.
Liu, J-H. Wang, Z. Zhang, H. Jiang, S. Huang, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, S-S.
Sheu, S-H. Li, H-Y. Lee, S-C. Chang, S. Yu, M-F. Chang, A 28nm 64Kb
Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro
for AI Edge Chips, 2020 IEEE
International Solid-State Circuits Conference (ISSCC), Feb. 2020. [23]
C-X.
Xue, T-Y. Huang, J-S. Liu, T-W. Chang, H-Y. Kao, J-H. Wang, T-W. Liu, S-Y.
Wei, S-P. Huang, W-C. Wei, Y-R. Chen, T-H. Hsu, Y-K. Chen, Y-C. Lo, T-H. Wen,
C-C. Lo, R-S. Liu, Chih-Cheng Hsieh,
K-T. Tang, M-F. Chang, A 22nm 2Mb ReRAM Compute-in-Memory Macro with
121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices, 2020 IEEE International Solid-State
Circuits Conference (ISSCC), Feb. 2020. [24]
X.
Si1, Y-N. Tu, W-H. Huang, J-W. Su, P-J. Lu, J-H. Wang, T-W. Liu, S-Y. Wu, R.
Liu, Y-C. Chou, Z. Zhang, S-H. Sie, W-C. Wei, Y-C. Lo, T-H. Wen, T-H. Hsu,
Y-K. Chen, W. Shih, C-C. Lo, R-S. Liu, Chih-Cheng
Hsieh, K-T. Tang, N-C. Lien, W-C. Shih, Y. He, Q. Li, M-F. Chang,
A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI
Edge Chips, 2020 IEEE International Solid-State Circuits
Conference (ISSCC), Feb. 2020. [25]
[Invited] Tzu-Hsiang Hsu,
Yen-Cheng Chiu, Wei-Chen Wei, Yun-Chen Lo, Chung-Chuan Lo, Ren-Shuo Liu,
Kea-Tiong Tang, Meng-Fan Chang, and Chih-Cheng
Hsieh, AI Edge Devices Using Computing-In-Memory and
Processing-In-Sensor: From System to Device, 2019 IEEE International Electron Devices Meeting (IEDM), Dec.
2019. [26]
Tzu-Hsiang
Hsu, R.-S. Liu, C.-C. Lo, K.-T. Tang, M.-F. Chang, and Chih-Cheng Hsieh, A 0.5V Real-time Computational CMOS
Image Sensor with Programmable Kernel for Always-on Feature Extraction, 2019 IEEE Asian Solid-State Circuits
Conference (ASSCC), Nov. 2019. [27]
Yi-Hsuan
Lin and Chih-Cheng Hsieh,
An Energy-Efficient 12b 20MS/s Time-Interleaved SAR ADC Using Shared
Semi-Resting DAC Switching, 2019 IEEE
International Conference on Analog VLSI circuits (AVIC), Oct. 2019. [28]
K.-T.
Tang,
W.-C. Wei, Z.-W. Yeh, T.-H. Hsu, Y.-C. Chiu, C.-X. Xue, Y.-C. Kuo, T.-H. Wen,
M.-S. Ho, C.-C. Lo, R.-S. Liu, Chih-Cheng
Hsieh and M.-F. Chang, Considerations of Integrating Computing-In-Memory
and Processing-In-Sensor into Convolutional Neural Network Accelerators for
Low-Power Edge Devices, 2019 IEEE
Symposia on VLSI Circuits (VLSI Symposia), Jun. 2019. [29]
Yung-Te Chang, Min-Rui Wu, Chih-Cheng Hsieh, A 40MS/S 12-Bit Zero-Crossing Based
SAR-Assisted Two-Stage Pipelined ADC with Adaptive Level Shifting, 2019 IEEE International Symp. on Circuits
and Systems (ISCAS), May. 2019. [30]
You-Shin
Chen, Tzu-Hsiang Hsu, Chien-Wen Chen, and Chih-Cheng Hsieh, A Current-Mode Differential Sensing CMOS
Imager for Optical Linear Encoder, 2019
IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2019. [31]
C-X.
Xue, W-H. Chen, J-S. Liu, J-F. Li, W-Y. Lin, W-E. Lin, J-H. Wang, W-C. Wei,
T-W. Chang, T-C. Chang, T-Y. Huang, H-Y. Kao, S-Y. Wei, Y-C. Chiu, C-Y. Lee,
C-C. Lo, Y-C. King, C-J. Lin, R-S. Liu, Chih-Cheng
Hsieh, K-T. Tang, M-F. Chang, A 1Mb Multibit ReRAM
Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for
CNN-Based AI Edge Processors, 2019 IEEE
International Solid-State Circuits
Conference (ISSCC), Feb. 2019. [32]
X.
Si1, J-J. Chen1, Y-N. Tu1, W-H. Huang, J-H. Wang, W-C. Wei, S-Y. Wu, X. Sun,
R. Liu, S. Yu, R-S. Liu1, Chih-Cheng
Hsieh, K-T. Tang, Q. Li, M-F. Chang, Twin-8T SRAM Computation-In-Memory
Macro for Multiple-Bit CNN- Based Machine Learning, 2019 IEEE International Solid-State Circuits Conference (ISSCC),
Feb. 2019. [33]
Kwuang-Han Chang, and Chih-Cheng Hsieh, A
Calibration-Free 0.7-V 13-bit 10-MS/s Full-Analog SAR ADC with
Continuous-Time Feedforward Cascaded (CTFC) Op-Amps, 2018 IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2018. [34]
Hsiang-Lin
Chen, Sung-En Hsieh, Tzu-Hsiang Hsu, and
Chih-Cheng Hsieh, A CMOS
Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient
Interference Rejections, 2018 IEEE
Asian Solid-State Circuits Conference (ASSCC), Nov. 2018. [35]
H
Chen,
Y-C Chang, S-R Yeh, Chih-Cheng Hsieh,
K-T Tang, P-H Hsieh, Y-T Liao, R Perumel, J-F
Chuang, C-C Chang, Y-C Chen, S. H. Chen, S-E Hsieh, Y-P Chen, Y-T Chen, T-H
Liu, Y-M Chang, W-C Lai, C-Y Wu, Y-H Chen, Y-C Weng, Development of a
Multisite, Closed-loop Neuromodulator for the Theranosis
of Neural Degenerative Diseases, 2018
IEEE Symposia on VLSI Circuits (VLSI Symposia), Jun. 2018. [36]
Sung-En
Hsieh and Chih-Cheng Hsieh,
A 0.4V 13b 270kS/s SAR-ISDM ADC with an Opamp-Less
Time-Domain Integrator, 2018 IEEE International Solid-State Circuits
Conference (ISSCC), Feb. 2018. [37]
W-H.
Chen, K-X. Li, W-Y. Lin, K-H. Hsu, P-Y. Li, C-H. Yang, C-X. Xue, E-Y. Yang,
Y-K. Chen, Y-S. Chang, T-H. Hsu, Y-C. King, C-J. Lin, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, M-F.
Chang, A 65nm 1Mb Nonvolatile Computing-in-Memory ReRAM Macro with
Sub-16ns Multiply-and-Accumulate for Binary DNN AI Edge Processors, 2018 IEEE International Solid-State
Circuits Conference (ISSCC), Feb. 2018. [38]
Chen-Che
Kao, Sung-En Hsieh, and Chih-Cheng
Hsieh, A 0.5V 12-bit SAR ADC using Adaptive Time-Domain Comparator
with Noise Optimization, 2017 IEEE
Asian Solid-State Circuits Conference (ASSCC), Nov. 2017. [39]
Ting
Liao, Nien-An Lee, and Chih-Cheng
Hsieh, A CMOS Time of Flight (TOF) Depth Image Sensor with In-Pixel
Background Cancellation and Sensitivity Improvement Using Phase Shifting
Readout Technique, 2017 IEEE Asian
Solid-State Circuits Conference (ASSCC),
Nov. 2017. [40]
Tzu-Hsiang
Hsu, and Chih-Cheng Hsieh,
Wen-Hsu Chang, Hann-Huei Tsai and Chin-Fong Chiu, A CMOS Imaging Platform
Using Single Photon Avalanche Diode Array in Standard Technology, 2017 IEEE Sensors Conference, Oct.
2017. [41]
[Invited] Chih-Cheng Hsieh and Albert
Yen-Chih Chiou, Low-voltage High-dynamic-range CMOS Imager with Energy
Harvesting, 2016 International Workshop
on Image Sensors and Imaging Systems (IWISS), Nov. 2016. [42]
Kuan-Lin
Liu, Sheng-Yeh Lai, Chin-Fong Chiu, and Chih-Cheng
Hsieh, A Time Delay Multiple Integration Linear CMOS Image Sensor for
Multispectral Satellite Telemetry, 2016
IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2016. [43]
Albert
Yen-Chih Chiou, Sung-En Hsieh, Yan-Quan Pan, Chia-Chi Kuo, and Chih-Cheng Hsieh, An
Integrated CMOS Optical Sensing Chip for Multiple Bio-Signal Detections, 2016 IEEE Asian Solid-State Circuits
Conference (ASSCC), Nov. 2016. [44]
Kwuang-Han Chang, and Chih-Cheng Hsieh, A 12 bit 150
MS/s 1.5 mW SAR ADC with Adaptive Radix DAC in 40
nm CMOS, IEEE Asian Solid-State
Circuits Conference (ASSCC),
Nov. 2016. [45]
Sung-En
Hsieh and Chih-Cheng Hsieh,
A 0.44fJconversion-step 11b 600KSs SAR ADC with Semi-Resting DAC, 2016 IEEE Symposia on VLSI Circuits (VLSI
Symposia), Jun. 2016. [46]
Sung-En
Hsieh and Chih-Cheng Hsieh,
A 0.3V 0.705fJ/Conversion-step 10-bit SAR ADC with Shifted Monotonic
Switching Scheme in 90nm CMOS, 2016
IEEE International Symp. on Circuits and Systems (ISCAS), May. 2016. [47]
Pei-Chen
Lee, and Chih-Cheng Hsieh,
A 0.4V 1.94fJ/Conversion-Step 10b 750kS/S SAR ADC with Input-Range-Adaptive
Switching, 2016 IEEE International
Symp. on Circuits and Systems (ISCAS),
May. 2016. [48]
Kwuang-Han Chang, and Chih-Cheng Hsieh, A 12b 10MS/s
18.9fJ/Conversion- step Sub-radix-2 SAR ADC, 2016 IEEE International Symposium on VLSI Design, Automation and
Test (VLSI-DAT), Apr. 2016. [49]
Chia-Chi
Kuo, and Chih-Cheng Hsieh,
A 132dB DR Readout IC with Pulse Width Modulation for IR Focal Plane Arrays, 2015 IEEE Asian Solid-State Circuits
Conference (ASSCC), Nov. 2015. [50]
Albert
Yen-Chih Chiou, and Chih-Cheng
Hsieh, A 0.4V Self-Powered CMOS Imager with 140dB Dynamic Range and
Energy Harvesting, 2015 IEEE Symposia
on VLSI Circuits (VLSI Symposia), Jun. 2015. [51]
Chih-Hao
Lin, and Chih-Cheng Hsieh,
A Dual-Mode CMOS Imager for Free-Space Optical Communication with Signal
Light Source Tracking and Background Cancellation, 2015 International Image Sensor Workshop (IISW), Jun. 2015. [52]
Sung-En
Hsieh, Cheng-Kang Ho, and Chih-Cheng
Hsieh, A 1.2V 1MS/S 7.65fJ/Conversion-Step 12-Bit Hybrid SAR ADC with
Time-to-Digital Converter, 2015 IEEE
International Symp. on Circuits and Systems (ISCAS), May. 2015. [53]
Jin-Yi
Lin, Kwuang-Han Chang, Chen-Che Kao, Shih-Chin Lo,
Yan-Jiun Chen, Pei-Chen Lee, Chi-Hui Chen, Chin Yin, and Chih-Cheng Hsieh, An 8-bit Column-Shared SAR ADC for CMOS
image Sensor Applications, 2015 IEEE
International Symp. on Circuits and Systems (ISCAS), May. 2015. [54]
Zheng-Wei
Huang, Chin-Fong Chiu and Chih-Cheng
Hsieh, An In-pixel Equalizer with kTC Noise
Cancellation and FPN Reduction, 2015
IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2015. [55]
[Invited] Chih-Cheng Hsieh, Chin Yin,
Albert Yen-Chih Chiou and Chih-Lin Lee, Design of Low-voltage Low-Power CMOS
Imager, 2014 Asian Image Sensors and
Imaging Systems Symposium (AISISS), Dec. 2014. [56]
Yan-Jiun
Chen, and Chih-Cheng Hsieh,
A 0.4V 2.02fJ/Conversion-step 10-bit Hybrid SAR ADC with Time-domain
Quantizer in 90nm CMOS, 2014 IEEE
Symposia on VLSI Circuits (VLSI Symposia), Jun. 2014. [57]
Shih-Wen
Chiu, Jen-Ho Wanf, Kwuang-Han
Chang, Hiang-Chiu Wu, Hsin Chen, Chih-Cheng Hsieh, Meng-Fan
Chang, Guoxing Wang, Kea-Tiong Tang, A signal
acquisition and processing chip with built-in cluster for chemiresistive
gas sensor array, 2014 IEEE
International New Circuits and Sysytems Conference (NEWCAS),
Jun. 2014. [58]
Chih-Hao
Lin, Che-Chun Lin, Ren-Jr. Chen, and Chih-Cheng
Hsieh, A Dual-Mode CMOS Image Sensor for Optical Wireless
Communication, 2014 IEEE International
Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2014. [59]
K-T.
Tang, S-W. Chiu, C-H. Shih, C-L. Chang, C-M. Yang, D-J. Yao, J-H. Wang, C-M.
Huang, H. Chen, K-H. Chang, Chih-Cheng.
Hsieh, T-H. Chang, M-F. Chang, C-M. Wang, Y-W. Liu, T-J. Chen, C-H.
Yang, H. Chiueh, J-M. Shyu, "A 0.5V 1.27mW
Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia," 2014 IEEE International Solid-State
Circuits Conference (ISSCC), Feb. 2014. [60]
Chin
Yin, and Chih-Cheng Hsieh, A
0.5V 34.4uW 14.28kfps 105dB Smart Image Sensor with Array-level Analog Signal
Processing, 2013 IEEE Asian Solid-State
Circuits Conference (ASSCC),
Nov. 2013 [61]
[Invited] Chih-Cheng Hsieh, Chin Yin,
Albert Yen-Chih Chiou and Chih-Lin Lee, Low-voltage Low-power and Smart CMOS
Image Sensor, 2013 Asian Symposium on
Advanced Image Sensors and Imaging Systems in Hamamatsu, Oct. 2013. [62]
Hsin-Han
Chen, and Chih-Cheng Hsieh,
An Inverter-based Capacitive Trans-impedance Amplifier Readout with Offset
Cancellation and Temporal Noise Reduction for IR Focal Plane Array, 2013 International Symposium on
Photoelectronic Detection and Imaging (ISPDI), June. 2013 [63]
Chin
Yin, and Chih-Cheng Hsieh,
A 1V 14kfps Smart CMOS Imager with Tracking and Edge-detection Modes for
Biomedical Monitoring, 2013 IEEE
International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2013 [64]
Chang-Yuan
Liou, and Chih-Cheng Hsieh,
A 2.4-to-5.2fJ/Conversion-step 10b 0.5-to-4MS/s SAR ADC with Charge Average
Switching DAC in 90nm CMOS, 2013 IEEE
International Solid-State Circuits Conference (ISSCC), Feb. 2013 [65]
[Invited] Chih-Cheng Hsieh and Meng-Ting
Chung, An Ultra-Low Voltage CMOS Imager with Novel Pulse-Width-Modulation
Readout, 2012 International Display
Workshops (IDW), Dec. 2012 [66]
Chuan-Hung
Hsiao, Wei-Lin Chen, and Chih-Cheng
Hsieh, A 0.8 V 80.3 dB SNDR Stage-Shared GU Modulator with
Chopper-Embedded Switched-Opamp for Biomedical
Application, 2012 IEEE Asian
Solid-State Circuits Conference (ASSCC),
Nov. 2012. [67]
Jin-Yi
Lin, Hsin-Yuan Huang, Chih-Cheng
Hsieh, and Hung-I Chen A 0.05mm2 0.6V 500kS/s 14.3fJ/Conversion-step
11-bit Two-step Switching SAR ADC for 3-Dimensional Stacking CMOS Imager, 2012 IEEE Asian Solid-State Circuits
Conference (ASSCC), Nov. 2012. [68]
Jui-Hsin
Chang, Kuo-Wei Cheng, Chih-Cheng
Hsieh, Wen-Hsu Chang, Hann-Huei Tsai and Chin-Fong Chiu, Linear CMOS
Image Sensor with Time-Delay Integration and Interlaced Super-Resolution
Pixel, 2012 IEEE Sensors Conference,
Oct. 2012. [69]
Wei-Fan
Chou, Shang-Fu Yeh, and Chih-Cheng
Hsieh, A 143dB 1.96% FPN Linear-Logarithmic CMOS Image Sensor with
Threshold-Voltage Cancellation and Tunable Linear Range, 2012 IEEE Sensors Conference, Oct. 2012. [70]
Shan-Ju
Tsai, Yen-Chun Chen, Chih-Cheng
Hsieh, Wen-Hsu Chang, Hann-Huei Tsai and Chin-Fong Chiu, A
Column-Parallel SA ADC with Linearity Calibration for CMOS Imagers, 2012 IEEE Sensors Conference, Oct.
2012. [71]
Hsin-Yuan
Huang, Jin-Yi Lin, Chih-Cheng Hsieh,
Wen-Hsu Chang, Hann-Huei Tsai and Chin-Fong Chiu, A 9.2b 47fJ/Conversion-Step
Asynchronous SAR ADC with Input Range Prediction DAC Switching, 2012 IEEE International Symp. on Circuits
and Systems (ISCAS), May. 2012. [72]
Kuo-Wei
Cheng, Chin Yin, Chih-Cheng Hsieh,
Wen-Hsu Chang, Hann-Huei Tsai and Chin-Fong Chiu, Time-Delay Integration
Readout with Adjacent Pixel Signal Transfer for CMOS Image Sensor, 2012 IEEE International Symposium on VLSI
Design, Automation and Test (VLSI-DAT),
Apr. 2012. [73]
Meng-Ting
Chung and Chih-Cheng Hsieh,
A 0.5V 4.95µW 11.8fps PWM CMOS Imager With 82dB Dynamic Range and 0.055%
Fixed-Pattern-Noise, 2012 IEEE
International Solid-State Circuits Conference (ISSCC), Feb. 2012. [74]
Kea-Tiong
Tang; Shih-Wen Chiu; Meng-Fan Chang; Chih-Cheng
Hsieh*; and Jyuo-Min Shyu, A wearable
Electronic Nose SoC for healthier living, 2011
IEEE Biomedical Circuits and Systems Conference (BioCAS),
Nov. 2011. [75]
Chin-Lin
Lee and Chih-Cheng Hsieh, A
0.8V 64x64 CMOS Imager with Integrated Sense-and-Stimulus Pixel for
Artificial Retina Applications, 2011
IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2011. [76]
Shang-Fu
Yeh, Chih-Cheng Hsieh,
Chiao-Jen Cheng and Chun-Kai Liu, A Novel Single Slope ADC Design for Wide
Dynamic Range CMOS Image Sensors, 2011
IEEE Sensors Conference, Oct. 2011. [77]
Lo-Wei
Huang, Chih-Cheng Hsieh,
Wen-Hsu Chang*, Ying-Zong Juang* and Chin-Fong Chiu*, A 1.8V Readout
Integrated Circuit with Adaptive Transimpedance Control Amplifier for IR
Focal Plane Arrays, 2011 IEEE Sensors
Conference, Oct. 2011. [78]
Chin
Yin, Chih-Cheng Hsieh,
Wen-Hsu Chang*, Ying-Zong Juang* and Chin-Fong Chiu*, An Information Sensor
with In-Pixel-Processing for Geriatric Nursing, 2011 IEEE Sensors Conference, Oct. 2011. [79]
Shang-Fu
Yeh, Jin-Yi Lin, Chih-Cheng Hsieh,
Ka-Yi Yeh* and Chung-Chi Jim Li*, A New CMOS Image Sensor Readout Structure
for 3D Integrated Imagers, 2011 IEEE
Custom Integrated Circuits Conference (CICC), Sep. 2011. [80]
Chin-Lin
Lee and Chih-Cheng Hsieh, A
0.6V CMOS Image Sensor with in-Pixel Biphasic Current Driver for Biomedical
Application, 2011 IEEE International
Symp. on Circuits and Systems (ISCAS),
pp. 1455-1458, May. 2011. [81]
Tsan-Jieh Chen, Chih-Hui Weng, Herming
Chiueh*, Chih-Cheng
Hsieh*, Shang-Fu Yeh, Wen-Hsu Chang, Ying-Zong Juang, Hann-Huei Tsai and
Chin-Fong Chiu, The Prototype of Real-Time Image Pre-Processing System for
Satellites' Remote Sensing, 2011 IEEE
International Symp. on Circuits and Systems (ISCAS), pp. 1992-1996, May. 2011 [82]
Shang-Fu
Yeh, Chih-Cheng Hsieh,
Chin-Fong Chiu, and Hann-Huei Tsai, An Image Lag Free CMOS Image Sensor with
Constant-Residue Reset, 2011 IEEE
International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2011. [83]
Sung-Min
Chin and Chih-Cheng Hsieh,
A New Rail-to-Rail Comparator with Adaptive Power Control for Low Power SAR
ADCs in Biomedical Application, 2010 IEEE
International Symp. on Circuits and Systems (ISCAS), pp. 1575-1578, May. 2010. [84]
Chih-Cheng Hsieh, Wei-Yu Chen, and
Chung-Yu Wu, A High Performance Linear Current Mode Image Sensor, 2009 IEEE International Symp. on Circuits
and Systems (ISCAS), pp.
1273-1276, May. 2009. [85]
Chih-Cheng
Hsieh, Chung-Yu Wu, Far-Wen Jih, Tai-Ping Sun and Horng Chang, A New
CMOS Readout Circuit Design for the IR FPA with Adaptive Gain Control and
Current-Mode Background Suppression, 1996
IEEE International Symp. on Circuits and Systems, vol. 1, pp. 137-140,
May. 1996. [86]
Chih-Cheng
Hsieh, Chung-Yu Wu, Far-Wen Jih, Tai-Ping Sun and Sheng-Jenn Yang, A
New Switch-Current Integration Readout Structure for Infrared Focal Plane
Array, Infrared Technology XX,
Proc. SPIE, vol. 2269, pp. 718-726, Jul. 1994. [87]
Chung-Yu Wu,
Chih-Cheng Hsieh, Far-Wen Jih, Tai-Ping Sun and Sheng-Jenn Yang, A
New Share-Buffered Direct-Injection Readout Structure for Infrared Detector, Infrared Technology XIX, Proc. SPIE,
vol. 2020, pp. 57-64, 1993. |
|
|
|
國內會議 (Local conference) |
|
[1]
Hung-Po
Kuo, Chih-Cheng Hsieh, A
12-BIT 150MS/S PIPELINED-SAR ADC WITH LOW DC GAIN AMPLIFIER” 2023 VLSI Design/CAD Symposium, Kaohsiung,
Taiwan, Aug. 1-4, 2023. [2]
Bao-Shu
Liu, Chih-Cheng Hsieh, A
Low-OSR 5th-Order Noise Shaping SAR ADC in a Two-Amplifier EF-EF-CIFF
Structure with Low-Noise PVT-Robust V-T-V Converters, 2023 VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 1-4, 2023. [3]
Hsin
Yu, Chih-Cheng Hsieh, A
53mK-NETD Low Power ROIC for 80*60 Microbolometer CMOS Thermal Image Sensor
with Ultra High Dynamic Range, 2022
VLSI Design/CAD Symposium, Virtual Meeting, Taiwan, Aug. 2-5, 2022. [4]
Min-Ruei Wu, Chih-Cheng
Hsieh, A 400KS/s 62.6pJ/c.-s 10-bits Column-Parallel Hybrid ADC Using
Self-Adaptive Charge-Injection Cell and Single-Slope Conversion, 2022 VLSI Design/CAD Symposium,
Virtual Meeting, Taiwan, Aug. 2-5, 2022. [5]
Chih-Cheng
Chen, Chih-Cheng Hsieh, A
12-ENOB 2nd-order Noise Shaping SAR ADC with Voltage-Time-Voltage Converter, 2021 VLSI Design/CAD Symposium,
Virtual Meeting, Taiwan, Aug. 4-7, 2021. [6]
Yu-Tang
Shen, Chi-Chun Chang, Yu-Hsiang Huang, Min-Yang Chiu, Guan-Cheng Chen, Chih-Cheng Hsieh, A 12-bit
350-kS/s Column-Parallel Single-Slope ADC Readout Circuit Using Charge-Pump
Phase-Locked Loop and Double-Edge Triggered Gray Code Counter, 2020 VLSI Design/CAD Symposium,
Taichung, Taiwan, Aug. 4-7, 2020. [7]
Wei-Chih
Lai, Chih-Cheng Chen, Chih-Cheng
Hsieh, A 12-bit SAR ADC with Reference Voltage Ripple Suppression, 2020 VLSI Design/CAD Symposium,
Taichung, Taiwan, Aug. 4-7, 2020. [8]
[Best Paper Award] Tzu-Hsiang Hsu, Chih-Cheng Hsieh, A 0.5V
Real-time Computational CMOS Image Sensor with Programmable Kernel for
Always-on Feature Extraction, 2019 VLSI
Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 6-9, 2019. [9]
You-Shin
Chen, T.-H. Hsu, C.-W. Chen, Chih-Cheng
Hsieh, A Low Noise Optical Encoder with Background Light Cancellation
Using Photodiodes in Series, 2019 VLSI
Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 6-9, 2019. [10]
Yi-Hsuan
Lin, Chih-Cheng Hsieh, An
Energy-Efficient 12b 20MS/s Time-Interleaved SAR ADC, 2019 VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 6-9,
2019. [11]
Min-Yang
Chiu, Guan-Cheng Chen, Tzu-Hsiang Hsu, Chih-Cheng
Hsieh, A 64x64 Pixels CMOS Image Sensor Using Pseudo Multiple
Sampling with Column CDS, 2018 VLSI
Design/CAD Symposium, Tainan, Taiwan, Aug. 7-10, 2018. [12]
Hsiang-Lin
Chen, Sung-En Hsieh, Tzu-Hsiang Hsu, Chih-Cheng
Hsieh, A CMOS Imager for Reflective Pulse Oximeter with Motion
Artifact and Ambient Interferer Rejection, 2018 VLSI Design/CAD Symposium, Kenting, Taiwan, Aug. 7-10, 2018. [13]
[Best Paper Award] Min-Rui Wu, Sung-En
Hsieh, Chih-Cheng Hsieh, A
12-bit SAR ADC with split switching DAC, 2018
VLSI Design/CAD Symposium, Kenting, Taiwan, Aug. 7-10, 2018. [14]
[Best Paper Award] Kwuang-Han Chang, Chih-Cheng Hsieh, A
5.3fJ/conv.-step 12b 50MS/s Full-Analog SAR ADC in 40nm CMOS, 2017 VLSI Design/CAD Symposium,
Kenting, Taiwan, Aug. 2-5, 2017. [15]
Albert Chiou, Chih-Cheng Hsieh, A 0.4V CMOS
Imager with Adaptive-Multiple-Sampling Linear Response, HDR Imaging, and
Energy Harvesting, 2017 VLSI Design/CAD
Symposium, Kenting, Taiwan, Aug. 2-5, 2017. [16]
Tzu-Hsiang
Hsu, Chih-Cheng Hsieh, A
Testing CMOS Image Sensor with High Sensitive Single
Photon Avalanche Diode Array, 2017 VLSI
Design/CAD Symposium, Kenting, Taiwan, Aug. 2-5, 2017. [17]
[Paper Award] Kwuang-Han Chang, Chih-Cheng Hsieh, A 12b
150MS/s 1.5mW SAR ADC with Adaptive Radix in 40nm CMOS, 2016 VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 2-5,
2016. [18]
[Paper Award] Albert Chiou, Sung-En
Hsieh, Yan-Quan Pan, Chia-Chi Kuo, Chih-Cheng
Hsieh, An Integrated CMOS Optical Sensing Chip for Multi-Bio-Signal
Detections, 2016 VLSI Design/CAD
Symposium, Kaohsiung, Taiwan, Aug. 2-5, 2016. [19]
[Best Paper] Chin Yin, Chin-Fong Chiu, Chih-Cheng Hsieh, A 32-stage 15-bit
Digital Time-delay-integration Linear CMOS Image Sensor with Data Prediction
Switching Technique, 2015 VLSI
Design/CAD Symposium, Hualien, Taiwan, Aug. 4-7, 2015. [20]
Pei-Chen
Lee, Chih-Cheng Hsieh, A
0.4V 1.94fJ/conversion-step 10b 750kS/s SAR ADC with Input-Range-Adaptive
Switching, 2015 VLSI Design/CAD
Symposium, Hualien, Taiwan, Aug. 4-7, 2015. [21]
Chia-Chi
Kuo, Chih-Cheng Hsieh, A
1.8V 128dB DR Capacitive Trans-impedance Amplifier Readout Circuit for IR
Focal Plane Arrays, 2015 VLSI
Design/CAD Symposium, Hualien, Taiwan, Aug. 4-7, 2015. [22]
Jui-Hsin
Chang, Chin-Fong Chiu, Chih-Cheng
Hsieh, A 12-stage Linear CMOS image sensor with APST-based Time Delay
Integration, 2014 VLSI Design/CAD
Symposium, Taichung, Taiwan, Aug. 5-8, 2014. [23]
Zeng-Wei
Huang, Chin-Fong Chiu, Chih-Cheng
Hsieh, A Time- of- Flight CMOS Image Sensor with 54% Fixed Patten
Noise Reduction, 2014 VLSI Design/CAD
Symposium, Taichung, Taiwan, Aug. 5-8, 2014. [24]
Sung-En
Hsieh, Ho-Cheng Kang, Chih-Cheng
Hsieh, A 12-bit SAR ADC with Voltage-to-Time Converter, 2014 VLSI Design/CAD Symposium,
Taichung, Taiwan, Aug. 5-8, 2014. [25]
Chin-Lin
Lee, Chih-Cheng Hsieh, A
Dual-Supply High Dynamic Range Sense-and-Stimulus Imager for Artificial
Retina Applications, 2013 VLSI
Design/CAD Symposium, Kaoshiung, Taiwan, Aug.
6-9, 2013. [26]
Chin
Yin, Chih-Cheng Hsieh, A
0.5V 34.4gW 105dB Smart Image Sensor with Array-level Analog Signal
Processing, 2013 VLSI Design/CAD
Symposium, Kaoshiung, Taiwan, Aug. 6-9, 2013. [27]
Chen-Che
Kao, E-Yuan Chang, and Chih-Cheng
Hsieh, A Linear-Logarithmic CMOS Image Sensor with FPN Reduction for
High Dynamic Range Applications, 2013
VLSI Design/CAD Symposium, Kaoshiung, Taiwan,
Aug. 6-9, 2013. [28]
Sheng-Hang
Su, Wei-Lin Chen, Chih-Cheng Hsieh,
Wen-Hsu Chang, Hann-Huei Tsai, and Chin-Fong Chiu, A 10-bit Column-Parallel
SAR ADC with Calibration for Sensor Array Applications, 2013 Symposium on Engineering, Medicine, and Biology Applications
(SEMBA), Tainan, Taiwan, Feb. 1-3, 2013. [29]
Po-Wei
Chang, Chin Yin, Chih-Cheng Hsieh,
Wen-Hsu Chang, Hann-Huei Tsai, and Chin-Fong Chiu, A Wide Dynamic Range CMOS
Image Sensor with Dual Exposure Readout for Biomedical Imager, 2013 Symposium on Engineering, Medicine,
and Biology Applications (SEMBA), Tainan, Taiwan, Feb. 1-3, 2013. [30]
Chuan-Hung
Hsiao, Wei-Lin Chen, and Chih-Cheng
Hsieh, A 0.7-V 81-dB DR Stage-Shared SC GU Modulator with
Chopper-Embedded Switched-Opamp for Biomedical
Application, 2012 VLSI Design/CAD
Symposium, Kengting, Taiwan, Aug. 7-10, 2012. [31]
Hsin-Yuan
Huang, Pei-Chen Lee, Chi-Hui Chen, Yi-Ting Tseng, and Chih-Cheng Hsieh, A 17.4fJ/c-s 0.9V 10-bit 1MS/s Low-Power
Asynchronous Successive Approximation Register Analog to Digital Converter, 2012 VLSI Design/CAD Symposium, Kengting, Taiwan, Aug. 7-10, 2012. [32]
Wei-Fan
Chou, Shang-Fu Yeh, and Chih-Cheng
Hsieh, A Linear-Logarithmic CMOS Image Sensor with FPN Reduction and Tunable Response Curve, 2012 VLSI Design/CAD Symposium, Kengting, Taiwan, Aug. 7-10, 2012. [33]
Kuo-Wei
Cheng, Chin Yin, Chih-Cheng Hsieh,
Wen-Hsu Chang, Hann-Huei Tsai and Chin-Fong Chiu, Design of Time-Delay Integration CMOS Readout
with Adjacent Pixel Signal Transfer, 2012
Symposium on Engineering, Medicine, and Biology Applications (SEMBA),
Taichung, Taiwan, Feb. 11-13, 2012. [34]
Chin Yin, Chih-Cheng Hsieh, Wen-Hsu
Chang, Ying-Zong Juang and Chin-Fong Chiu, An Information Sensor with
In-Pixel-Processing for Geriatric Nursing, 2011 VLSI Design/CAD Symposium, Yunlin, Taiwan, Aug. 2-5, 2011. [35]
Hsin-Yuan Huang, Chih-Cheng Hsieh, Wen-Hsu Chang, Hann-Huei Tsai and
Chin-Fong Chiu, A 10b Rail to Rail 500KS/s A SAR ADC with Reduced DAC
Switching technique and Adaptive Settling Pulse for Biomedical Applications, 2011 VLSI Design/CAD Symposium,
Yunlin, Taiwan, Aug. 2-5, 2011. [36]
Shang-Fu
Yeh, Jin-Yi Lin, Chih-Cheng Hsieh,
Ka-Yi Yeh and Chung-Chi Jim Li, A New CMOS Image Sensor Design for 3D
Integrated Imagers, 2011 VLSI
Design/CAD Symposium, Yunlin, Taiwan, Aug. 2-5, 2011. [37]
Chih-Lin
Lee and Chih-Cheng Hsieh, A
0.8V 64x64 CMOS Imager with Integrated Sense-and-Stimulus Pixel for
Artificial Retina Applications, 2011
Symposium on Engineering, Medicine, and Biology Applications (SEMBA),
Yunlin, Taiwan, Jul. 8-10, 2011. [38]
Shang-Fu
Yeh, Chih-Cheng Hsieh,
Ka-Yi Yeh and Chung-Chi Jim Li, A Wide Dynamic Range CMOS Image Sensor for
Bio-Applications, 2011 Symposium on
Engineering, Medicine, and Biology Applications (SEMBA), Yunlin, Taiwan,
Jul. 8-10, 2011. [39]
Chin-Lin
Lee and Chih-Cheng Hsieh, A
Pulse Frequency Modulation CMOS Image sensor for Biomedical Application, 2010 VLSI Design/CAD Symposium,
Kaohsiung, Taiwan, Aug. 3-6, 2010. |
|
|
|
專利發表 |
|
申請中案件 [1]
Chih-Cheng Hsieh, Shang-Fu Yeh, Ka-Yi Yeh, and
Chung-Chi Jim Li, The Circuit Architecture and Timing
Diagram for 3-D CMOS Image Sensor. |
|
|
|
(A) USA PATENT LIST |
|
1.
Chih-Cheng Hsieh Regulated-Cascode Amplifier with
Clamping circuit, USA Patent 6377120, Apr. 2002. 2.
Chien-Chang Huang, Chih-Cheng Hsieh, Solid-state image
sensor for improving sensing quality and manufacturing method thereof, USA
Patent 7169633, Jan. 2007. 3.
Chih-Cheng Hsieh, Readout circuit with on-sensor-chip two-dimensional interpolation,
USA Patent Application US-2004-0051800, Mar. 2004. 4.
Chih-Cheng Hsieh, Method and apparatus for defect compensation in an image
sensor, USA Patent Application US-2004-0212705, Oct. 2004. 5.
Chih-Cheng Hsieh, Chien-Chang Huang, Image sensing device for improve image
quality and reducing color shift effect, USA Patent Application
US-2005-0230597, Oct. 2005. 6.
Chih-Cheng Hsieh, Integrated auto-focusing device, USA Patent Application
US-2005- 0247854, Nov. 2005. 7.
Chih-Cheng Hsieh, Integrated image capturing device, USA Patent Application
US-2005- 0253958, Nov. 2005. 8.
Chih-Cheng Hsieh, Active pixel sensor with isolated photo-sensing region and
peripheral circuit region, USA Patent Application US-2006- 0017830, Jan.
2006. 9.
Ming-Chun Su, Chien-Chang Huang, Chih-Cheng Hsieh, Method for
controlling well capacity of a photodiode, USA Patent Application US-2006-
0275940, Dec. 2006. 10.
Chien-Chang Huang, Chih-Cheng Hsieh, Ching-Wei
Chen, Pinned photodiode sensor with gate controlled SCR transfer switch and
method of formation, USA Patent Application US-2006- 0249764, Nov. 2006. 11.
Ching-Wei Chen, Chih-Cheng Hsieh, Chien-Chang Huang, CMOS image sensor,
USA Patent Application US-2007-0102739, May. 2007. 12.
Ching-Wei Chen, Chih-Cheng Hsieh, Chien-Chang Huang, Method for
fabricating CMOS image sensor, USA Patent Application US-2007- 0092986, Apr.
2007. 13.
Chih-Cheng Hsieh, Image sensor and sensing method thereof, USA Patent
Application US20120205520 A1, Aug. 2012. 14.
Chih-Cheng Hsieh, Circuit sharing time delay integrator, USA Patent 8704580,
April. 2014. 15.
Chih-Cheng Hsieh, Pixel array module with self-test function and method thereof,
USA Patent 9007078, April. 2015. 16.
Chih-Cheng Hsieh, Optical recognition system and method thereof, USA Patent
9029753, May. 2015. 17.
Chih-Cheng Hsieh, Processing device for position sensing, USA Patent
2020/0204128 A1, Jan. 2020. 18.
Chih-Cheng Hsieh, Image sensor integrated with convolutional neural network
computation circuit, USA Patent 11770642, 2023 19.
Chih-Cheng Hsieh, Image sensor chip and sensing method thereof, USA Patent
11785353, 2023 |
|
|
|
(B) TAIWAN
PATENT LIST |
|
1.
謝志成, “夾鉗式調整型串級增益放大器電路,” R.O.C. Patent 145965. 2.
謝志成, “防止感測裝置產生高亮度反轉效應之獲取影像訊號方法,” R.O.C. Patent 14691. 3.
謝志成, “可增加藍光響應之光電二極體,” R.O.C. Patent 163549. 4.
謝志成, “具有多型態電路佈置之光電二極體的互補式金屬氧化半導體電晶體影像感應器,” R.O.C. Patent 164411. 5.
謝志成, “影像感測裝置及其調整影像畫面速率之方法,” R.O.C. Patent 176123. 6.
謝志成, “可防止感測陣列在長時間曝光產生固定暗帶圖樣方法,” R.O.C. Patent 177915. 7.
謝志成, “切換式電容電路之動態補償技術,” R.O.C. Patent 178846. 8.
謝志成, “可防止曝光強度過強產生不對稱耦合效應的感測裝置,” R.O.C. Patent 180402. 9.
謝志成, “可減少漏電流影響之光電二極體,” R.O.C. Patent 197048. 10. 謝志成, “在感測晶片上具有二維內插功能信號讀出電路,” R.O.C. Patent 199118. 11. 謝志成, “信號讀出單元以及運用該信號讀出單元之積體電路,” R.O.C. Patent 220362. 12. 謝志成, “彩色影像之缺陷補償方法及裝置,” R.O.C. Patent 220360. 13. 謝志成, “減少不均勻光感測效應之影像感測器,” R.O.C. Patent 236546. 14. 謝志成, “一種整合式的影像擷取裝置,” R.O.C. Patent 237992. 15. 謝志成, “整合式影像擷取晶片,” R.O.C. Patent 242369. 16. 謝志成, “在曝光時間改變時使畫面連續之方法及其影像感測裝置,” R.O.C. Patent 245552. 17. 謝志成, “可加強感測效果之影像感測器及其製造方法,” R.O.C. Patent 253597. 18. 謝志成, “控制感光二極體之光電荷量之方法,” R.O.C. Patent 256730. 19. 謝志成, “具有閘極控制SCR傳導開關之鉗制型光二極體感測元件,” R.O.C. Patent 266429. 20. 謝志成, “具省電功能之影像感測裝置及其省電方法,” R.O.C. Patent 271094. 21. 謝志成, “影像感測器及其感測方法,” R.O.C. Patent I424746. 22. 謝志成, “具共用電路的時間延遲積分器結構” R.O.C. Patent I434571. 23. 謝志成, “具有自我測試的像素陣列模組及其自我測試方法” R.O.C. Patent I457575. 24. 謝志成, “類比數位轉換控制器及數位校正方法” R.O.C. Patent I544749. 25. 謝志成, “生理訊號感測晶片及其生理訊號感測方法” R.O.C. Patent I 587836. 26.
謝志成, “整合卷積神經網路運算電路的影像感測器” R.O.C. Patent I 786992 27.
謝志成, “影像感測晶片及其感測方法” R.O.C. Patent I 805358 |