ALU-4 Bit-8 Function 1. Objectives

• To design ALU by VHDL

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• To familiarXilinx CAD Tool

( Using Command File to Simulation)
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• To create main VHDL file to link all component

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2. Pre-Discussion

• ALU-4 Bit-8 Function Table
• ALU4-8 VHDL file
• Command file for simulation
• Simulation Step :

1. Editing command file
2. select sim signal
3. click FILE => click "run script file"
       => run [*.cmd] file
4. obtain the sim wave => save to *.jpg
      e.g. n789-u880999-sim wave
5. upload to server : 
    only one file (don't include Dir.), 
    e.g. : n789aluWave.jpg

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3. Experimental

• ALU Function Block (4 bit, 8 function)
• Digilab XL FPGA Pinout
• Conponent U1 : Hex2ssd
• Conponent U2 : ALU4-8 (new)
• Conponent U3 : Clk-Gen
• Conponent U4 : MUX41
• Conponent U5 : DEC24
• *.vhd refer to server : Lab01ref
• upload to server : 
      only one file (don't include Dir.), 
      e.g. : n789aluMain.vhd
• Demo to TA

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4. Project

• Design ALU with 8 bits - 4 function(add, sub, AND, OR)

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5. Post-Discussion

• 4 bit ALU (4 function : ADD, SUB, AND, OR)

e.g.  0x2 ADD 0x3 = 0x5  => 4ssd_display :  2   abgf_seg   3   5
e.g.  0x2 SUB 0x3 =  - 0x1  => 4ssd_display :  2   g&d_seg   3   1(d-seg : nagative) e.g.  0x2 AND 0x3 = 0x2  => 4ssd_display :  2   egc_seg   3   2
e.g.  0x2 OR 0x3 = 0x2  => 4ssd_display :  2   egc_seg   3   3
e.g.  0xF ADD 0xF = 0x1E  => 4ssd_display :  2   abgf&h_seg   3   E (h-seg : carry)
e.g.  0x3 SUB 0x2 = +0x1  => 4ssd_display :  3   g_seg   2   1
input : use  sw1 ~ sw8, btn1 ~ 4

• Drawfunction block diagram to implement above spec.

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